Ultra compact, 32-bit, RISC core processor: 12.5K Gates 16/32-bit RISC with 8-bit size and power characteristics

The Synopsys ultra-compactDesignWare® ARC™ 601 confi gurable core is a usercustomizable 32-bit microprocessor that implements the DesignWare ARCompact instruction set architecture (ISA. In the DesignWare ARCompact ISA, compact 16-bit encodings of frequently used statically occurring 32-bit instructions are defined. These can be freely intermixed with the 32-bit instructions in the DesignWare ARC 601 core increasing throughput and simplifying program flow. CPU Architecture
5-stage instruction pipeline
Static branch prediction
32-bit data, instruction and address buses, 24-bit instruction address space
Scoreboarded data memory pipeline to reduce data stalls
Single-cycle instruction CCM (Closely Coupled Memory), 1KB - 512KB
Single-cycle data CCM, 2KB - 16KB
Configurable endianness
Up to 32, two-level interrupts
ARCompact™ ISA
16- and 32-bit instructions for high code density
No overhead for switching between 16- and 32-bit
Single-cycle instruction execution
Up to 128 dual or single operand instruction codes available for user-defined extensions
Up to 64 directly addressable core registers and
32 conditional execution codes
Flexible addressing modes
Registers
16 or 32 entry register file in base processor, extendible to 60
26 general purpose registers, extendible to 54
32-bit auxiliary register-space for single-cycle, unarbitrated data storage and retrieval
Power Management
Sleep mode via software instruction
Clock gating option
High-efficiency pipeline
On-chip RAM controls
Host Interface/Debug Features
Software and hardware breakpoints with cascadable triggers
JTAG interface to host tools
Debug host can access all registers and CPU memory
Supported by leading debuggers, including Green Hills Software and MetaWare®
System Interface
Configurable port complies with industry-standard AMBA or BVCI
Slave interfaces exposed for loading optional instruction and data CCMs