Synchronous, High-density, Single-Port-SRAM (SP-SRAM): SH Type
Innopower provides the synchronous high-density Single-Port-SRAM (SP-SRAM): The SH-type compiler, for various processes. Single-port SRAM can be incorporated with the Innopower standard cell library. Different combinations of words, bits, and aspect ratios can be used to generate the most desirable configurations. In certain process, Innopower provides the SP-SRAM compiler with the option of row redundancy.
Synchronous Single-port Register File (1PRF): SY Type
Innopower provides the synchronous single-port register file (1PRF): The SY-type compiler, for various processes. Different combinations of words, bits, and aspect ratios can be used to generate the most desirable configurations. 1PRF is most suitable for the high speed but relatively small configurations, such as the CPU, high-speed data buffer, and communications.
Given the desired size and timing constraints, the Innopower memory compiler is capable of providing the suitable synchronous SRAM layout instances within minutes. It automatically generates the data sheets, Verilog/VHDL behavioral simulation models, P & R (place-and-rout) models, and the test patterns to be used in the ASIC designs. The length of duty cycle can be neglected as long as the setup/hold times and the minimum high/low pulse widths are satisfied. This provides a more flexible CK falling edge during each operation. Both the word write and the byte write operations are supported.
- Supports synchronous read and write operations
- Low leakage current and low AC power
- One read/write port
- Supports fully-customized layout density
- Supports automatic power-down mechanism to eliminate DC current
- Clocked address inputs, CSB, WEB, and DI to the RAM at the CK rising edge
- Supports byte write and word write operations
- Selective aspect ratios to best-fit chip floor plan
- Includes Verilog/VHDL timing simulation model generators
- Includes SPICE netlist generator
- Includes GDSII layout generator
- Supports BIST code