UMC 55nm SP Logic Process 2-port register file memory compiler with power gating feature

Synchronous Two-Port Register File (2PRF): SZ Type

Innopower provides the synchronous two-port register file (2PRF): The SZ-type compiler, for various processes. 2PRF can be incorporated with the Innopower standard cell library. Different combinations of words, bits, and aspect ratios can be used to generate the most desirable configurations. The 2PRF is designed for one read port and one write port, respectively. It is most suitable for the high-speed applications, such as the cache, high-speed data queue, and communication applications.

Synchronous, High-density/High-performance, Two-Port-SRAM (2P-SRAM): SB Type and SW Type

Innopower provides the synchronous, high-density, Two-Port-SRAM (2P-SRAM): SB-type compiler; and/or synchronous, high-performance, Two-Port-SRAM: The SW-type compiler, for certain processes. 2P-SRAM can be incorporated with the Innopower standard cell library. The 2P-SRAM is designed for one read port only.

Given the desired size and timing constraints, the Innopower memory compiler is capable of providing the suitable synchronous 2PRF/2P-SRAM layout instances within minutes. It automatically generates the data sheets, Verilog/VHDL behavioral simulation models, P & R (place-and-rout) models, and the test patterns to be used in the ASIC designs. The length of duty cycle can be neglected as long as the setup/hold times and the minimum high/low pulse widths are satisfied. This provides a more flexible CK falling edge during each operation. Both the word write and the byte write operations are supported.