The USB 2.0 HSIC PHY is a complete mixed-signal transceiver macro-cell that implements the USB 2.0 High Speed Inter Chip (HSIC) layer for USB 2.0 High Speed Device and Host applications.
The USB 2.0 HSIC PHY consists of a logic macro, which is available as either hard or soft IP, and a hard-IP block that contains the special driver circuit that is mandated by the HSIC specification.
The HSIC standard exists because there are many applications where it makes sense to embed a subsystem that uses USB 2.0 within embedded applications that do not need to be connected to external devices.
The USB 2.0 HSIC PHY can be used for subsystems within a smartphone. The big advantage over conventional USB2 is the elimination of most of the power consumption and most of the chip area that would be required for conventional USB2 PHYs.
- 8-bit (optionally 16-bit) parallel UTMI+ interface
- Built-in Self Test
- Scan-based DFT
- 1.2V±10% driver supply
- Design files kit
- Extensive documentation: