Implements the USB 3.0 Host or Device functionality, interfacing with most third party USB 3.0 PHY’s and either an AHB, AXI or OCP bus interface.
Host functionality is supported using high performance DMA engine configured to support full xHCI implementations for use in standard PCIe-USB bus adaptors/chip sets or be configured with a subset of features for embedded applications requiring limited host functionality. The controller also supports Device functionality operating in a cut through mode.
The Dual Mode Controller core is partitioned to support standard power management schemes including clock gating and multiple power wells.
- Compliant with USB3.0 Specification Rev1.0
- Compliant with xHCI Rev1.0
- Compliant with USB Specification Rev 2.0
- Compliant with USB2.0 Link Power Management
- Configurable USB2.0 PHY Interface
- DMA engine for device mode functionality.
- Configurable core frequency: 125, 250, 500 Mhz.
- Configurable PIPE Interface for USB3.0 PHY
- Endpoint zero processor block for processing standard requests for device mode functionality
- Native packet interface
- Simple Register Interface for internal Register Access
- Pin or SW selectable between host/device
- Highly modular and configurable synchronous design
- Extensive clock gating support
- Multiple Power Well Support
- Software control for key features
- Optional USB2.0 Core for Backward Compatibility
- Application Interface – AHB, AXI, PCIe
- xHCI Engine with configurable number of device slots, interrupters, interrupt moderation, configurable scratchpad support, optional support for host initiated stream data movement and optional debug capability etc
- Device mode with configurable number of endpoints, configurable endpoint types, including support for bulk streaming endpoints, optional endpoint zero processor block, optional proprietary descriptor based DMA engine with configurable endpoint FIFOs.
- RTL Source Code
- Test bench, Test cases and behavioral models
- Protocol checkers, bus watchers and performance monitors
- Design Guide
- Verification Guide
- Synthesis Guide