USB 3.0 PHY supporting all four USB speeds (LS, FS, HS, SS)
- On board scope and diagnostics for fast system verification
- Supports popular 90nm and 130nm processes
- Extremely low power consumption per lane resulting in significant savings. . .
- USB 3.0 PHY supporting all four USB speeds (LS, FS, HS, SS).
- Single GDSII.
- Available in popular advanced foundry processes.
- Excellent performance margin and receiver sensitivity
- GDSII layout and layer map files, LEF of pin size and locations, LVS netlist in HSPICE format and LVS report, DRC report.
- Simulation model for digital blocks, Behavioral models for analog blocks.
- Synopsysí PrimeTime STA results, Gate-level netlist and SDF timing file. DesignWare USB 3.0 PHY Databook. BSDL files for JTAG AC/
- DC Boundary Scan, ATE test vectors
Video Demo of the USB 3.0 PHY - TSMC 40LP25 x1
Synopsys Demonstrates SuperSpeed USB 3.0 Interoperability