The USB 3.0 SuperSpeed OTG controller IP is compliant with OTG&EH3.0. The USB 3.0 OTG controller is able to dynamically swap host/peripheral roles while operating at SuperSpeed using Role Swapping Protocol (RSP) as defined in OTG&EH3.0 specification. The IP is capable of handling multiple devices when acting as Host.
USB3.0 PIPE interface
Support 8/16/32 data bus width
AXI, AHB, PLB Bus standards
Support 32/64 bit data bus
Supports RSP – Role Swap Protocol
Hub Class support and supports multiple System bus interfaces – AXI/AXI/PLB with 32/64 bit data bus
Supports Super Speed OTG communication
Support USB3 power down modes
Support Control, Bulk, Isochronous and Interrupt transaction
Configurable up to 15 transmit and 15 receipt endpoints apart from default endpoint
Dynamically configurable Endpoint FIFO for optimum usage of memory
Synchronous SRAM interface for FIFO
Integrated DMA controller
Fully Synthesizable RTL code
SystemVerilog based verification environment.
Synthesis constraints and scripts files
User Manual and verification Document.
Programmer model document
Synthesis constraints and scripts files.
Block Diagram of the USB 3.0 SuperSpeed OTG controller IP Core
Video Demo of the USB 3.0 SuperSpeed OTG controller IP Core
USB 3.0 Device Controller Demo
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