The USB 3.0 Device Controller IP Core is a highly configurable core and implements the USB 3.0 device functionality and can be interfaced with third party USB 3.0 PHY’s.
The USB 3.0 Device Controller IP Core can be configured to support any allowed number of Bulk, Isochronous and Interrupt endpoints. Control endpoints can be supported natively by the core or optionally by an external processor.
The USB 3.0 Device Controller IP Core is architected with a high performance DMA engine and application interface for maximizing performance of streaming data, and can be easily adapted to support limited host functionality, if required. Optionally, the core can also be configured to operate with customer’s DMA.
The USB 3.0 Device Controller IP Core supports all defined USB 3.0 power states. The design is carefully partitioned to support standard power management schemes. Optionally, it can be configured to manage power mode transitions of the controller and the USB 3.0 PHY for aggressive power savings required for mobile and handheld devices.
The controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as AXI, AHB, OCP etc as well as standard off-chip interconnects. Its flexible backend interface makes it easy to be integrated into wide range of applications.
The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology.
- USB 3.0 Compliant
- Implements All Layers
- Supports Interrupt /Bulk/Isochronous/Control Transfers
- LFPS Support
- Supports Aggressive Low Power Management
- Configurable Core Frequency.
- Flexible User Application Logic which can be used by any SoC / OCP interface.
- User Application Logic has Optional DMA controller with configurable buffers sizes or Optional Standard FIFO Interface, in absence of DMA controller.
- User Application Logic has Optional Endpoint Zero Block for processing the Standard Device Descriptor
- Configurable Datapath on User Application Interface (32/64/ 128 bit)
- Support for various Hardware and Software Configurability regarding Core characteristics.
- Configurable number of Configurations, Interfaces, Alternative Interfaces and endpoints.
- USB2.0 Backward Compatibility.
- Synthesizable Verilog RTL
- Configurable System Verilog Verification IP
- Synthesis Scripts
Block Diagram of the USB 3.0 Device Controller IP Core