A highly configurable core that implements the USB 3.0 Host functionality that can be interfaced with third party USB 3.0 PHY’s.
Supports all mandatory and optional features of the xHCI power management interface. The design is carefully partitioned to support standard power management schemes. Optionally, it can be configured to manage power mode transitions of the controller and the USB 3.0 PHY for aggressive power savings required for mobile and handheld devices. Designed with a high performance DMA engine in the xHCI Interface for maximizing performance. Interfaces such as AXI, AHB, OCP or PCIe core with optional virtualization support, for standard host adaptor implementations.
- Implements Phy Logical/ Link / Protocol Layers.
- Asynchronous clocking between Host Controller and Application logic
- Supports Aggressive Low Power Management
- Configurable core frequency: 125, 250, 500 Mhz.
- Configurable PIPE Interface: 8, 16, 32 bit.
- Configurable Buffer Sizes.
- Configurable Host Controller Engine
- Support for normative optional features
- Support for multi-port implementation
- Flexible User Application Logic
- Can be used by any SoC / OCB interface.
- PCIe with optional IOV support
- Configurable Datawidth: 32, 64, 128 bit.
- Simple Register Interface for internal Register Access.
- Synthesizable Verilog RTL
- Configurable System Verilog Verification IP.
- Synthesis Scripts