This macro is a TSMC 65LP implementation of the physical layer (PHY) of the SuperSpeed (5.0 Gbps) USB 3.0 function, as specified in the Universal Serial Bus 3.0 Specification Revision 1.0. The macro consists of three major modules which are common, transmitter, and receiver blocks and supports the five power LTSSM states (Disabled, U0-U3) specified in the USB 3.0 standard. Power islands are also implemented to minimize standby power and the macro only requires a 1.2V core power supply. The macro operates from 0șC to 125șC in a wire-bond package.
- Conforms to the PHY description in the Universal Serial Bus 3.0 Specification Revision 1.0
- Serial data rate of 5.0 Gbps
- On-chip PLL accepts a wide range of reference clock frequencies between 14MHz and 60MHz.
- Built in spread spectrum clock generation.
- 4-tap adaptive decision feedback equalization with adaptive CTLE and offset correction.
- Robust clock/data recovery tracks the USB 3.0 static frequency offset of +/- 300 PPM, in addition to the spread spectrum offset of 0 to - 5000 PPM.
- On demand eye / bathtub curve measurement capability.
- Simple 16 bit bus interface for programming parameters
- BIST functions for manufacturing test including multiple pattern generator/error detector
- Analog Test Bus for test and characterization
- GDSII physical layout of Macro
- Behavioral (Verilog) Model of Macro
- Abstract (lef/def)
- Timing model (.lib)
- CDL netlist
- Macro Datasheet