Sidense's SLP NVM IP is based on a one-time programmable (OTP), patent pending, anti-fuse technology that is one of the smallest and fastest in the industry. It requires no additional mask layers, no special voltages to be programmed and is portable across several different technology nodes and foundries, including TSMC, UMC, SMIC, GLOBALFOUNDRIES, Tower, IBM and Fujitsu. The OTP memory can be programmed in the field, at wafer or during production testing. Sidense's SLP products are targeted to standard logic digital CMOS processes at 180nm.
It is an extremely viable solution for MASK ROM, eFuse and discrete/embedded FLASH replacement.
- Densities from 128 bits to 256 Kbits
- Macros may be tiled for higher densities
- Word Widths from 8 to 128 bits
- Access Times down to 26 nS
- Secure Program Lock Function
- Built-in Redundancy and Repair
- Mask ROM Option - single layer change
- Can mix ROM and field-programmable OTP on same macro
- Optional differential and redundant read modes
- Serial or Parallel Data Access
- No additional Masks or Process Steps
- Very low power
- Very Dense
- Highly Secure
- Fast Access Times
- Flexible Architecture
- Low-Voltage operation
- Hard Macro with all support files including datasheets, verilog and LIB models, design integration and application notes, LVS netlist, hard macro placement in LEF, and GDSII file.