VHDL Reference CAN

Features

• Supports CAN protocol version 2.0 part A, B
• Flexible test bench environment
• Simulates entire CAN bus system (number of nodes defined by user)
• Test program set can be extended by user
• Run time information stored in trace file
• Generation of pattern files supported

Benefits

• Most widely spread tool for verification of VHDLbased CAN implementations
• Reduces risk to fail CAN conformance test

Deliverables

• Detailed User’s Manual
• Example of an implementation for fast start-up
• Well documented source code
• Tested with Synopsys VSS, Mentor Graphics QuickHDL, Mentor Graphics ModelSim
• Prepared for porting to other VHDL simulators

Block Diagram of the VHDL Reference CAN