Virtex-5 APU Floating Point Unit

Features

• Compliant with the IEEE-754 standard for single and double-precision floating-point arithmetic, with minor and documented exceptions
• Decodes and executes standard PowerPC floating-point instructions
• Optimized for 2:1 APU:CPU clock ratio, allowing PowerPC to operate at maximum frequency
• Uses autonomous instruction issue to hide arithmetic latency and decrease cycles per instruction
• Optimized implementation leverages Virtex-5 high-performance DSP features
• Integrated into Xilinx Embedded Development Kit (EDK) design flow