Functionality
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1. Accept 25Mhz, 36MHz, 40MHz input crystal
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External compatibility and integration requirements
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1. should also accept pad voltage CMOS clock as alternative to XO.
2. support CMOS, CMOS differential and CML differential outputs.
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Timing or Performance requirements
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1. jitter and phase noise should not exceed 5ps.
2. power up transient to availability of clock should be constrained (<1ms)
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Technology Requirements
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TSMC 40nm LP
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Availability Timing
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This is currently a feasibility search. no timeline but preference for available IP with silicon proven performance.
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Support requirement
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IP integration, verification, and post-silicon bringup.
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Quality requirement
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jitter and phase noise <5ps
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Business Scheme Requirement
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Need to be small and low power for cost optimization
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