Wideband Ultra High-Speed DDC IP Core

Features

• Ultra high-performance wideband digital downconverter (DDC)
• Supports Virtex-II and Virtex-II Pro FPGAs
• Fits in Virtex-II XC2V3000 or larger
• Similar to the TI GC1012B with enhanced features
• Dual demultiplexed inputs for 16-bit real or 16-bit complex (I and Q) data
• Maximum input data rate of 280 MSPS
• Maximum input bandwidth of 140 MHz (real inputs) or 280 MHz (complex inputs)
• Fully programmable dual NCO with 32-bit frequency and phase offset control
• NCO delivers > 110 dB SFDR
• Decimation settings of 2, 4, 8, 16, 32, and 64 for complex output
• Decimation settings of 1, 2, 4, 8, 16, and 32 for real output
• Dual decimating FIR filter features up to 1792 taps
• User-programmable 18-bit FIR filter coefficients
• Default FIR filter coefficients for 80% and 90% filters
• Output formatter delivers real, complex, offset, inverted data in 16 or 24 bits
• Test bench included
• Downloadable simulation model available
• Compatible with Xilinx Foundation ISE Tools

Deliverables

• The DDC Core 422 is implemented as a fixed netlist IP Core and is configured to be compatible with Xilinx Foundation ISE Core Generator software.
• When the core is generated in the Core Generator, it automatically adds all necessary netlist files and VHDL or Verilog templates to the project directory. Only the XCO core file will appear in the Xilinx Foundation ISE Project Navigator source file tree.
• Supplied with the core is a group of VHDL test bench files that can be used to verify functional operation. They demonstrate many of the operational modes, but can be easily modified by the user to vary the control settings.