XAUI PHY, TSMC 65GP, x8

The DesignWare® XAUI PHY IP is designed for use in any networking or high-end computing SoC solutions. Designed for the latest high-speed backplanes, the XAUI PHY supports the 10 Gigabit Ethernet standards that are commonly used in high-speed communications applications. Based on Synopsys' proven high-speed SerDes technology, the DesignWare XAUI PHY provides a cost effective and extremely low power solution that is designed to meet the needs of today's XAUI designs.
To handle increasing communication system speeds, the XAUI standard is designed to take a 10 Gbps serial stream and divided into four 2.5Gbps serial streams that run over copper traces and chip to chip connections using 8B10B coding at 3.125Gbaud. By taking advantage of copper links, higher performance communications applications can be cost effectively deployed.

The XAUI PHY integrates high-speed mixed-signal custom CMOS circuitry and is compliant with the XAUI base specification. While extremely low in power consumption and area requirements, Synopsys' XAUI PHY substantially exceeds the electrical specifications in such key performance areas as jitter and receive sensitivity.