40Gb/s MAC-SEC IP Core proven in Xilinx Virtex-7 FPGAs
Compliant to IEEE 802.1AEbw MACSEC XPN AES-256 Specification.
- 40Gb/s MAC-SEC IP Core proven in Xilinx Virtex-7 FPGAs
- 50 MPPs in Virtex7 FPGAs (XC7Vx690T-2) – Full Line Rate Encryption; Configurable to support any frame size from 64B – 9220B (Jumbo)
- GCM per 64-bit PN XPN-MACSEC (IEEE Update to MAC-SEC)
- Optional Counter-Mode & ESPv3 (IPSEC) 40Gb/s modes fully supported
- Dynamically select Key, State (SA), Mode on a per packet basis at line rate – No external Classifier/NPU or Memories required.
- Fully integrated FPGA based Line Rate Classifier with Ternary Match functionality (e.g. psuedo TCAM)
- Configurable number of pipeline stages in GCM and Algorithm cores
- Configurable intra-module pipeline stages on each interface to support various floor-plans
- Supports Technology Specific Builds (Virtex-7) or completely SOFT RTL build to support Technology Retargeting to ASIC or Altera FPGAs
- Fully scripted parallel compile supported using Vivado (2hrs)
- VHDL Source code w/SystemC & VHDL Verification Environments
- Reference Chip Design with 4x10GbE Interfaces provided with IP, along with C++ Software Driver API, Memory Map, Hardware Detail Design Reference Manual, and Requirements Traceability Matrix
- SystemC TLM 2.0 Model of IP core, and C++ standalone XPN-MACSEC model included
- Reference 1U ECU Test Platform with preconfigured 40Gb/s core in PCI-E Based V7-x690T-2 also available (4x10GbE SFP+ & QSFP+ optical interfaces)
- API Compatible with 100GbE & 10GbE ESS IP Cores
- Authentication, Confidentialiity, anti-replay protection of Layer-2 communications.
Block Diagram of the XPN-MACSEC AES-256 GCM 40Gb/s Encryption IP Core