Home | Products | Industry Articles | Latest News

The development of verification environments for today's system-on-a-chip (SoC) designs is becoming more and more complex. With increasing design complexity, large number of in-house and third-parties IPs, different protocols being used in the design, and limited resources design verification represents a bottleneck in product development process. Ultimate requirement is to have support and solutions from reliable verification solutions providers. This corner will bring to your attention the latest News, latest products, latest initiative in this field. Featured Products: SATA I SVC, Serial ATA (SATA) System Verification IP (NCQ, Port Multiplier / Selector) from ExpertIO, Inc SATA II SVC, Serial ATA II System Verification Component from ExpertIO, Inc FC SVC, Fibre Channel SVC Verification IP (Link, AL, FC10G) from ExpertIO, Inc SAS SVC, Serial SCSI (SAS) System Verification IP (Including optional STP support) from ExpertIO, Inc SATA PM/PS SVC, Serial ATA Port Multiplier / Port Selector test bench from ExpertIO, Inc Ethernet SVC, IEEE 802.3 Ethernet MAC and Phy (10Mb - 40Gb) Verification IP (MAC, 10/100/1000, XAUI, KX, KX4, KR, etc) from ExpertIO, Inc pcimaster_fx, PCI / PCI-X Master from Synopsys, Inc. usbhost_fz, Universal Serial Bus 2.0 Host from Synopsys, Inc. enethub_fx, IEEE 802.3 Hub from Synopsys, Inc. sio_txrx_vmt, Serial I/O TxRx from Synopsys, Inc. More ...

Latest News: eInfochips Announces VMM-Enabled MIPI CSI-2, DSI & HSI and SDIO Verification IP for the Synopsys DesignWare Verification IP Alliance Program (Jun. 30, 2009) Perfectus Announces Industry's First SystemVerilog-based OVM Tested ONFi Verification IP for ONFi 2.1 Specification (Jun. 22, 2009) eInfochips announces DDR2 SDRAM SystemVerilog & VMM based Memory Model Generator Tool (Jun. 02, 2009) Perfectus Announces Industry's First SystemVerilog-Based OVM Compliant SuperSpeed USB Verification IP for USB 3.0 Protocol (Feb. 26, 2009) Cadence Extends the Open Verification Methodology Beyond SystemVerilog to Include SystemC and e Language Support (Feb. 23, 2009) Industry Articles : Architecting the OCP uVC verification component (Jan. 13, 2009) Performance Verification Methods Developed for an HDTV SoC Integrating a Mixed Circuit-Switched / NoC Interconnect (STBus/VSTNoC) (Sep. 15, 2008) Learning not to fear PCI Express compliance (Aug. 12, 2008) Achieve PCIe compliance and interoperability in your IP core-based design (Jul. 14, 2008) Mixed-Signal Verification for USB 2.0 Physical Layer IP (Jun. 09, 2008)