 |
Cadence Announces Development of OVM Verification IP for USB 3.0 and PCI Express 3.0 High-Speed Protocols (Nov. 17, 2008)
Cadence Design Systems today announced the planned first quarter 2009 availability of new Open Verification Methodology (OVM) verification IP (VIP) for two key high-speed protocols: USB 3.0 and PCI Express 3.0. |
| |
VinChip announces USB 3.0 Verification IP for Super Speed USB Devices (Nov. 17, 2008)
VinChip today announced a Super Speed USB IP solution consisting of the Device Controller and Verification IP. The solution also includes a Super Speed USB test platform and Device Drivers in WinCE, Linux, and ECOS uCLinux to aid Firmware Development for Mass storage, Video and other applications. |
| |
nSys Announces Availability of FREE Evaluation licenses of USB 3.0 Verification Suite (Nov. 17, 2008)
The USB 3.0 nVS (nSys Verification Suite) is a complete verification solution consisting of Bus Function Model (BFM), Monitor, Checker and Test Suites for functional verification of all types of USB 3.0 based designs. The nVS allows design and verification engineers to quickly and extensively test the entire functionality of USB 3.0 compliant devices. |
| |
Denali Software Premieres Verification IP for the New SuperSpeed USB Interface (Nov. 10, 2008)
Denali today announced that its PureSpec™ verification intellectual property (VIP) product now supports the USB 3.0 specification from the USB 3.0 Promoter Group , allowing device and system designers to begin advanced USB 3.0 development. |
| |
eInfochips announces DDR2 SDRAM verification IP and Reed Solomon Encoder design IP (Nov. 06, 2008)
eInfochips today announced the availability of JEDEC (JESD79-2D) compliant DDR2 SDRAM verification IP and European DVB, IEEE 802.16, IESS, ETS 300 421 and ETS 300 429 standards compliant Reed Solomon encoder design IP. |
| |
Cadence Expands Portfolio of System-Level Verification IP and SpeedBridge Adapters to Boost Acceleration and Emulation Performance (Nov. 04, 2008)
The New System VIP and SpeedBridge Adapters Speed Up Time to Market and Improve Quality, Further Extending Cadence Leadership in VIP Portfolio Breadth and Depth |
| |
Silicon Interfaces announces the release of its Verification Methodology Manual (VMM) based USB 2.0 SystemVerilog Verification IP (Nov. 03, 2008)
The USB2.0 VIP is developed using SystemVerilog test benches based on VMM methodology using coverage-driven, constrained-random and assertion-based techniques. |
| |
Mentor Graphics Broadens Support of OVM Compliant Verification IP for IEEE802.3-2005 Gigabit Ethernet-based Designs (Oct. 30, 2008)
Mentor Graphics, today announced that its unique verification IP solution, the Questa® Multi-view Verification Component (MVC) library, has been extended to support the IEEE802.3-2005 Gigabit Ethernet standard. |
| |
Sonics OCP Library for Verification Now Shipping (Oct. 23, 2008)
Sonics today announced the general availability of the Sonics OCP Library for Verification (SOLV). Core designers are using the SOLV package for debugging, performance tuning and validation of complex intellectual property (IP) cores using OCP interfaces. |
| |
Silicon Interfaces announces the release of its Open Verification Methodology (OVM) Based Gigabit Ethernet MAC SystemVerilog OVC (Oct. 16, 2008)
Silicon Interfaces’ GEMAC core implements the Ethernet Media Access Control (MAC) protocol according to IEEE 802.3 specification. The MAC has a standard Gigabit Media Independent Interface (GMII) to connect to any PHY interface. |
| |
Cadence Expands Enterprise Verification IP Portfolio by 5X to Provide Industry's Broadest OVM Multi-Language Offering (Oct. 15, 2008)
VIP Portfolio Extends to Over 30 Industry-Standard Protocols, Enabling Customers to Improve Schedule Predictability, Productivity, and Product Quality |
| |
Silicon Interfaces announces its OVM Based IEEE 1394 Link Layer Controller Verification IP (Oct. 06, 2008)
Silicon Interfaces announces the availability of their OVM Based IEEE 1394-1995/1394a-2000 Link Layer Controller Open Verification Component (OVC) supporting multi-language verification environments. |
| |
Denali Software First to Announce Verification IP for PCI Express 3.0 Designs (Sep. 04, 2008)
Denali Software today announced the availability of PureSpec™ PCI Express™ (PCIe) verification intellectual property (VIP) product which now supports the latest version of the Gen 3 specifications from the PCI-Special Interest Group (PCI-SIG®), allowing chip designers to begin early Gen 3 development. |
| |
eInfochips announces MIPI SystemVerilog Verification IP (Aug. 04, 2008)
MIPI (Mobile Industry Processor Interface) VIP is a SystemVerilog component compliant to CSI-2 MIPI specification for Camera Serial Interface Version 1.00 and DRAFT MIPI Alliance Standard for D-PHY Version 0.85.00. |
| |
Synopsys' DesignWare Verification IP Enhanced to Support New SATA 6Gbps Specification (Jun. 18, 2008)
The DesignWare Verification IP supports all major simulators and verification languages including Verilog, SystemVerilog, VHDL and Vera, allowing designers to quickly and efficiently create a comprehensive SATA- based environment. In addition, the Verification IP for SATA delivers up to 5X performance improvement when used with Synopsys' VCS® simulation tool |
| |
eInfochips announces AVM 3.0 & OVM Compliant SystemVerilog AMBA AHB Verification IP (Jun. 13, 2008)
Integration of AMBA AHB AVM 3.0 Ensures Availability of OVM Compliant High-Quality Verification IP for Advanced SystemVerilog Verification |
| |
Cadence Delivers OVM-Compliant Verification IP (Jun. 09, 2008)
Cadence today announced the availability of the first two advanced testbench verification IP (VIP) products that are compliant with the Open Verification Methodology (OVM) |
| |
Denali Software Announces Availability of MMAV 2008 Verification IP (May. 22, 2008)
This latest package release provides a complete and an accurate solution for simulating memories, including support for most of the memory technologies, including DRAM, SRAM, Flash, and Card memories, and several standard protocols. |
| |
Arasan Chip Systems Introduces New Low Voltage SDIO Validation Platform (Apr. 16, 2008)
The new SD/SDIO Device HVP is a SD host platform tool based upon Arasan's SD/SDIO host controller used for SDIO device validation. Fully compliant with SD/SDIO v2.0, SD Memory v2.0, and MMC v4.3, the SD socket can interface to any standard SD or MMC card for fast validation. |
| |
nSys Offers World's Largest Portfolio of Verification IPs for OVM-Based SystemVerilog Environments (Feb. 19, 2008)
nSys announced today the availability of Verification IP products integrated with the Open Verification Methodology (OVM) environment. The nSys Verification IPs for OVM-based environments are available for standard interfaces such as AMBA AXI, Ethernet, PCIe, SATA, and USB etc |
| |
SoCVerify Kit by HDL Design House - HDL Design House announces its Verification IP (VIP) library (Feb. 19, 2008)
SoCVerify Kit covers a large number of standards and protocols such as I2C, HyperTransport, Serial Rapid IO, SATA, SAS, LPC, PCI, PCI-X, SPI4, SMBUS, PMBUS and each VIP constituting SoCVerify Kit library supports a wide set of verification methodologies such as: eRM, UVC, OVM. |
| |
Rockfish Technology Launches Interlaken Verification IP (Oct. 22, 2007)
The Interlaken BFM has an easy to use interface for the customer’s testbench consisting of a clocked data bus and control lines. Alternatively, Rockfish Technology offers a SystemVerilog packet based testbench for those customers needing a complete solution. |
| |
Silicon Interfaces announces the release of its IEEE 1394 uVC Verification IP using Cadence IPCM Universal Reuse Methodology (URM) (Oct. 19, 2007)
The IEEE 1394 Function Controller uVC verifies designs that include IEEE 1394 Function Controller. This uVC consists of a complete set of elements for stimulating, checking, and collecting coverage information for the IEEE 1394 protocol, as well as thoroughly exercises the link controller. |
| |
VinChip Announces Verification Testbench for Certified Wireless USB (Aug. 07, 2007)
The testbench includes a configurable functional model for Wireless USB Host, Device and WiMedia MAC. Certified Wireless USB testbench is purely Verilog based which assures our customer's Wireless USB core to be in line with the specifications. |
| |
OCP-IP Announces Support for Cadence's Assertion Based OCP Protocol Verification IP (Jul. 09, 2007)
OCP-IP today announced their support of Cadence’s Assertion Based Verification IP (ABVIP) for the development and verification of the OCP protocol. OCP’s ascendance as the system architecture “backbone” within increasingly complex consumer and portable designs has driven the need for improved verification at the block, chip and system levels. |
| |
ARM Unleashes Adaptive Verification IP For On-Chip Communication (Jun. 04, 2007)
Adaptive Verification IP combines the time-to-market advantages of automated verification with the quality of in-context, knowledge-based verification that was previously only possible manually. Adaptive Verification IP complements existing random or directed-random methods with a powerful new approach to reducing overall verification time, improving verification confidence, and enabling the explosion in SoC size and complexity to continue. |
| |
Avery Design Systems Announces Support for PCI Express IO Virtualization and AMBA AXI (May. 24, 2007)
PCI-Xactor support for the PCI Express IO Virtualization (IOV) and Address Translation Services (ATS) standards based on Single Root IOV (SR-IOV) will be available in June 2007 and Multi-Root IOV (MR-IOV) support is planned for H2'07 release. The solution is comprised of enhanced Root Complex, Endpoint, and Switch BFMs, protocol assertions, and a compliance test suite. |
| |
Silicon Interfaces announces the release of its new RapidIO Physical Layer Interface OpenVera Verification IP (May. 09, 2007)
Silicon Interfaces' RapidIO Physical Layer Interface OpenVera Verification IP is a fully documented, off the shelf component for the verification of the RapidIO Physical Layer Interface Controller. RapidIO is a Packet-switched Interconnect primarily intended for an Intra-system Interface for chip-to-chip and board-to-board communications at Gigabyte-per-second performance levels. |
| |
Denali Launches New Product to Speed System-On-Chip Verification (Apr. 16, 2007)
Denali Software today announced the availability of PureSpec(TM) SystemRDL, a verification IP (VIP) product that automates functional verification of configuration registers for system-on-chip (SoC) designs. |
| |
OCP-IP Standardizes on Synopsys' DesignWare Verification IP for OCP-IP's CoreCreator Verification Toolset (Apr. 10, 2007)
Synopsys and OCP-IP today announced that they are collaborating to provide Synopsys' DesignWare(R) Verification IP (VIP) as part of OCP-IP's CoreCreator verification toolset. |
