DDR Verification IP in native SystemVerilog (UVM/OVM/VMM)

Features

• DDR-Xactor Memory models support a full SDRAM/DIMM user API with many advanced features not included in many “free” models such as
• Clock jitter
• Random DQS timing
• CRC/parity error injection
• Backdoor access to DDR chip and DIMM memory locations
• Callbacks and analysis ports for memory access and state transitions
• DDR-Xactor supports
• Supports all sizes
• Supports all speed modes
• DDR3, DDR4
• LPDDR2-S2/S4/SX, LPDDR3-S2/S4/SX models
• RDIMM, UDIMM, SO-DIMM

Deliverables

• BFM components, Producer-Consumer scoreboard
• Complaince testsuites in source code format
• Compliance checklist test plan
• User Guide