Synopsys DesignWare® Verification IP (VIP) for PCI Express® provides a quick and efficient way to verify PCI Express designs. It is fully configurable to support verification of PCI Express endpoints, switches, and root complex devices. It can be configured for verification at multiple levels including the 8b/10b, and PIPE interfaces or at the serial interface using the supplied Serdes. It can be used to verify both MAC and PHY.
The DesignWare VIP for PCI Express supports the SystemVerilog design language and the Verification Methodology Manual (VMM).
The VMM defines a coverage driven methodology for SystemVerilog using a constrained random environment.
The DesignWare VIP for PCI Express is available in the DesignWare Library, the VCS Verification Library, and as an individual suite. It combines with the DesignWare digital IP core and PHY for PCI Express, to provide a complete solution for PCI Express designs.
- Up to eight virtual channels
- Full LTSSM (Link Training)
- Power management
- Automatic generation of flow control packets
- Provides single word read and write transfers to memory, I/O, and configuration space
- Generates block read and write transfers to memory space
- Verification at PIPE, 10b, and serial interface
- Automatic handling of Transaction, Data Link, and Physical layer tasks
- Supports x1, x2, x4, x8, x12, x16 lanes
- Full Requester and Completer functions