The Cadence Memory Models for HMC are ready-made for your environment, providing consistent results whether you are using Cadence Incisive®, Synopsys VCS®, or Mentor Questa® simulators. You have the freedom to build your testbench using any of these verification languages: SystemVerilog, e, Verilog, VHDL, or C/C++. Cadence Memory Models support the Universal Verification Methodology (UVM) as well as legacy methodologies.
- HMC Rev 1_1 specification is supported.
- Supports Link retry
- Supports Chaining
- Supports half-width link
- Supports link retraining
- Supports higher bandwidths
- Supports power state management