The Cadence Memory Models for HMC are ready-made for your environment, providing consistent results whether you are using Cadence Incisive®, Synopsys VCS®, or Mentor Questa® simulators. You have the freedom to build your testbench using any of these verification languages: SystemVerilog, e, Verilog, VHDL, or C/C++. Cadence Memory Models support the Universal Verification Methodology (UVM) as well as legacy methodologies.
- Supports spec version: HMC Rev 1_1
- Transaction callback events on requests and responses to monitor activity at each protocol layer
- Link layer initialization at power-on