MIPI CPHY Verification IP is compliant with MIPI CPHY specification and verifies CPHY devices. CPHY Verification IP is developed by experts who have worked on complex protocols before.
MIPI CPHY VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
- Supports MIPI CPHY Specification.
- Supports upt to 32 trio lanes.
- Supports to set symbol clock
- Supports to set lane skew between lanes in a trio for arrival of sot.
- Supports various kind of Tx and Rx errors generation and detection
- SoT error
- Sync error
- Sync length error
- Ecc error
- Supports PPI interface
- Supports both short and long packets
- Supports BTA operation and error injection in BTA
- Supports detection of all timeouts and injection of various timeout errors
- Supports both high speed and low power packet transmission and reception
- Supports fine grain control of timing parameters
- Monitor,Detects and notifies the testbench of all protocol and timing errors.
- Supports constraints Randomization.
- Status counters for various events in bus.
- Support PRBS test mode pattern generation and checking.
- Callbacks in transmitter and receiver for various events.
- MIPI CPHY Verification IP comes with complete test suite to test every feature of MIPI CPHY specification.
- Functional coverage for complete MIPI CPHY features.
- Faster testbench development and more complete verification of MIPI CPHY designs.
- Easy to use command interface simplifies testbench control and configuration of Tx,Rx and monitor
- Simplifies results analysis.
- Runs in every major simulation environment.
- Complete regression suite containing all the MIPI CPHY testcases.
- Examples showing how to connect various components, and usage of Tx,Rx and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.