The MIPI CSI-2 Verification IP is the industry’s most comprehensive protocol validation solution for predictable verification of MIPI DPhy based designs. MIPI CSI-2 VIP integrates automatic constrained random stimulus generation, assertion, protocol checking and functional coverage within a single extensible component.
MIPI CSI-2 VIP provides a simple yet powerful user interface. This drastically reduces the time and effort needed to create a verification environment to thoroughly verify and ensure first time right silicon. User can verify the complex design with few test cases in a very short time instead of running multiple directed test cases.
MIPI CSI-2 VIP is reusable, highly configurable, pre-verified. It provides plug and play System Verilog based verification environment. The VIP can be used for verifying any SOC incorporating MIPI CSI-2 Tx/Rx at module, chip and system level.
- Compliant to MIPI CSI-2 1.1-2012 specification
- Complaint to MIPI DPHY 1.1 specification
- Supports CSI-2 Transmitter and Receiver
- Supports short and long packets
- Supports PPI interface.
- Supports multiple data lines (upto 4)
- Supports image applications with varying pixel formats from 6 to 24 bits per pixel
- Supports all virtual channel identifier
- Supports Data Type value interleaving
- Supports virtual channel interleaving
- Supports Lane distribution and merging in case of Multi Lane functionality.
- Supports Error generation and detection.
- System Verilog encrypted/un-encrypted source code
- User guide and Release notes
- Sanity test cases
- Examples on topological usage
- Sample verification environment
Block Diagram of the MIPI CSI-2 Verification IP