The MIPI CSI-2 Verification IP is ready-made for your environment, providing consistent results whether you are using Cadence Incisive®, Synopsys VCS®, or Mentor Questa® simulators. You have the freedom to build your testbench using any of these verification languages: SystemVerilog, e, Verilog, VHDL, or C/C++. The Simulation VIP supports the Universal Verification Methodology (UVM) as well as legacy methodologies.
- The CSI-2 VIP supports the latest MIPI CSI-2, D-PHY and C-PHY specifications.
- Enables Transmitter and Reciever Design-Under-Test Configurations
- Provides Full Stack and Controller Only verification
- Includes Test Suite
- Full support of D-PHY 1.2, including 8 lanes and skew calibration.
- Full support of C-PHY 1.0.
- Verifies both CSI-2 receiver and transmitter.
- Supports one to eight D-PHY data lanes
- Supports D-PHY1.2 and C-PHY1.0 with both PHY interfaces (DpDn and PPI).
- Includes the MIPI D-PHY and C-PHY VIPs for physical layer verification.
- Industry's first CSI-2 VIP
- Part of the broadest line of MIPI simulation VIP
- Cadence has been a MIPI Alliance Contributing Member since 2007
- Features optional Accelerated VIP
Video Demo of the MIPI CSI-2 Verification IP (VIP) Verification IP
MIPI CSI-2 VIP Demo