MIPI CSI-2 Verification IP Provides the mobile industry a standard, robust, scalable, low-power, high-speed, cost-effective interface that supports a widerange of imaging solutions for mobile devices. MIPI CSI-2 Verification IP provides an smart way to verify the MIPI CSI-2 standard data transmission and control interfaces between transmitter and receiver. The SmartDV's MIPI CSI-2 Verification IP is fully compliant with version 1.00 MIPI Alliance specification for serial Interface and provides the following features.
MIPI CSI-2 VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
Features
- Supports 1.00 MIPI CSI-2 Specification.
- Supports data transmission interface (CSI-2) unidirectional differential serial interface.
- Supports control interface (CCI) two-wire,bi-directional,half duplex,serial interface used for controlling the transmitter.
- The CCI device supports all four different read operations
- Single read from random location
- Sequential read from random location
- Single read from current location
- Sequential read from current location
- The CCI device supports all two different write operations
- Single write to random location
- Sequential write starting from random location
- Supports the following register width
- 8-bit
- 16-bit
- 32-bit
- 64-bit
- Supports forward escape ULPM on all Data Lanes.
- Supports image applications with varying pixel formats from six to twenty-four bits per pixels.
- Supports short and long packets.
- Supports all types of short packets.
- Supports all types of long packets.
- Supports all lane configuration.
- Supports all virtual channel identifier.
- Supports various methods to interleave the transmission of different image data formats
- Interleaved data transmission using data type value
- Interleaved data transmission using virtual channels
- Supports various methods to interleave the data transmission using data type value
- Packet level interleaved data transmission
- Frame level interleaved data transmission
- Supports multiple packets per transmission.
- Supports differential and single ended mode of operation.
- Supports various kind of Tx and Rx errors generation and detection
- SoT error
- Sync error
- Word count error
- Sync length error
- Checksum error
- Ecc error
- Monitor,Detects and notifies the testbench of all protocol and timing errors.
- Supports constraints Randomization.
- Status counters for various events in bus.
- Callbacks in node transmitter, receiver and monitor for user processing of data.
- MIPI CSI-2 Verification IP comes with complete test suite to test every feature of MIPI CSI-2 specification.
- Functional coverage for complete MIPI CSI-2 features
Benefits
- Faster testbench development and more complete verification of MIPI CSI-2 designs.
- Easy to use command interface simplifies testbench control and configuration of Tx,Rx and monitor
- Simplifies results analysis.
- Runs in every major simulation environment.
Deliverables
- Complete source code of MIPI CSI-2 Monitor,Rx,Tx.
- Complete regression suite containing all the MIPI CSI-2 testcases.
- Examples's showing how to connect various components, and usage of Tx,Rx and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
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