The MIPI DPhy 1.1 Verification IP is the industry’s most comprehensive protocol validation solution for predictable verification of MIPI DPhy based designs. MIPI DPhy VIP integrates automatic constrained random stimulus generation, assertion, protocol checking and functional coverage within a single extensible component.
MIPI DPhy VIP provides a simple yet powerful user interface which drastically reduces the time and effort needed to create a verification environment to thoroughly verify and ensure first time right silicon. User can verify the complex design with few test cases in very short time instead of running multiple directed test cases.
MIPI DPhy VIP is reusable, highly configurable, pre-verified. It provides plug and play System Verilog based verification environment. The VIP can be used for verifying any SOC incorporating MIPI DPhy Tx/Rx at module, chip and system level.
- Compliant to MIPI DPhy 1.1 Specification.
- Supports one clock and upto 4 data Lanes
- Supports all kinds of error generation and detection.
- Supports PPI interface.
- Supports HS Mode for high speed data transactions and LP mode for control transactions.
- Supports flexibility to change the timing parameters.
- Support checking at PPI interface level.
- System Verilog source code
- User guide and Release notes
- Sanity test cases
- Examples on topological usage
- Sample verification environment
Block Diagram of the MIPI DPhy 1.1 Verification IP