The MIPI DSI Verification IP is the industry’s most comprehensive protocol validation solution for predictable verification of MIPI DPhy based designs. MIPI DSI VIP integrates automatic constrained random stimulus generation, assertion, protocol checking and functional coverage within a single extensible component.
MIPI DSI VIP provides a simple yet powerful user interface. This drastically reduces the time and effort needed to create a verification environment to thoroughly verify and ensure first time right silicon. User can verify the complex design with few test cases in a very short time instead of running multiple directed test cases.
MIPI DSI VIP is reusable, highly configurable, pre-verified. It provides plug and play System Verilog based verification environment. The VIP can be used for verifying any SOC incorporating MIPI DSI Tx/Rx at module, chip and system level.
- Compliant to MIPI DSI 1.2 specification.
- Complaint to MIPI DPHY 1.1 specification.
- Supports both DSI Host and Device.
- Supports MIPI DCS specification.
- Supports MIPI DBI specification.
- Supports MIPI DPI (Video mode) specification.
- Supports short and long packets
- Supports PPI interface.
- Supports multiple data lines (upto 4).
- Supports 4 virtual channels
- Supports Burst and Non-Burst Modes
- Supports Error generation and detection.
- Supports flexibility to change the timing parameters.
- System Verilog encrypted/un-encrypted source code
- User guide and Release notes
- Sanity test cases
- Examples on topological usage
- Sample verification environment
Block Diagram of the MIPI DSI Verification IP