MIPI DSI Verification IP provides an smart way to verify the MIPI DSI bi-directional two-wire bus. The SmartDV's MIPI DSI Verification IP is fully compliant with version 1.02 MIPI Alliance specification for serial Interface and provides the following features.
MIPI DSI VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
- Supports 1.02 MIPI DSI Specification.
- Full MIPI DSI Tx and Rx functionality.
- Supports MIPI DBI specification
- Supports MIPI DCS specification
- Operates as a Tx,Rx, or both.
- Monitor,Detects and notifies the testbench of all protocol and timing errors.
- Supports short and long packets
- Supports all types of short packets
- Supports all types of long packets
- Supports all lane configuration
- Supports multiple packets per transmission
- Supports differential and single ended mode of operation
- Supports PPI interface
- Supports all BTA commands
- Various kind of Tx and Rx errors generation and detection
- SoT error
- Sync error
- Word count error
- Sync length error
- Checksum error
- Ecc error
- Supports detection of all timeouts and injection of various timeout errors
- Supports both high speed and low power packet transmission and reception
- Supports fine grain control of timing parameters
- Status counters for various events in bus.
- Callbacks in node transmitter, receiver and monitor for user processing of data.
- MIPI DSI Verification IP comes with complete test suite to test every feature of MIPI DSI specification.
- Functional coverage for complete MIPI DSI features
- Faster testbench development and more complete verification of MIPI DSI designs.
- Easy to use command interface simplifies testbench control and configuration of Tx,Rx and monitor
- Simplifies results analysis.
- Runs in every major simulation environment.
- Complete source code of MIPI DSI Monitor,Rx,Tx.
- Complete regression suite containing all the MIPI DSI testcases.
- Examples's showing how to connect various components, and usage of Tx,Rx and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.