The Simulation VIP is ready-made for your environment, providing consistent results whether you are using Incisive®, Synopsys VCS®, or Mentor Questa® simulators. You have the freedom to build your testbench using any of these verification languages: SystemVerilog, e, Verilog, VHDL, or C/C++. Simulation VIP supports the Universal Verification Methodology (UVM) as well as legacy methodologies.
- Industry's first LLI VIP
- Part of the broadest line of MIPI simulation VIP
- has been a MIPI Alliance Contributing Member since 2007
- The LLI VIP supports MIPI Low-Latency Interface specification version 2.0.
- Enables Master and Slave Design-Under-Test Configurations
- Provides Full Stack and Controller Only verification
- Includes Test Suite
- Complies with MIPI LLI specification version 2.0.
- Supports PHY, PA, DLL, and transport layers.
- Supports PA PHIT, CRC, and SEQ automatic calculation and generation.
- Supports PHIT36 (extended data frames).
- Supports DLL message and transaction frame.
- Supports DLL flow control and mount/unmount procedure.