The MIPI MPhy 3.0 Verification IP is the industry’s most comprehensive protocol validation solution for predictable verification of MIPI MPhy based designs. MIPI MPhy VIP integrates automatic constrained random stimulus generation, assertion, protocol checking and functional coverage within a single extensible component.
MIPI MPhy VIP provides a simple yet powerful user interface. This drastically reduces the time and effort needed to create a verification environment to thoroughly verify and ensure first time right silicon. User can verify the complex design with few test cases in a very short time instead of running multiple directed test cases.
MIPI MPhy VIP is reusable, highly configurable, pre-verified. It provides plug and play System Verilog based verification environment. The VIP can be used for verifying any SOC incorporating MIPI MPhy Tx/Rx at module, chip and system level.
- Compliant to MIPI MPhy 3.0 specification.
- Supports both TYPE I and TYPE II module.
- Supports HS Mode and LS mode.
- HS Mode supports both A and B mode data rate with all ‘Gears’.
- LS Mode supports both PWM and SYS signaling mode.
- LS Mode supports all ‘Gears’.
- Supports protocol interfaces RMMI and SAP.
- Supports flexibility to configure lanes according to the requirement.
- Supports 8b/10b error insertion and detection.
- Supports 8b/10b Bypass mode.
- Supports random control symbol insertion. (Filler and Markers).
- Supports flexibility to change the timing parameters.
- Supports checking at the RMMI and SAP interface level.
- System Verilog source code
- User guide and Release notes
- Sanity test cases
- Examples on topological usage
- Sample verification environment
Block Diagram of the MIPI M-Phy Verification IP