The Simulation VIP is ready-made for your environment, providing consistent results whether you are using Incisive®, Synopsys VCS®, or Mentor Questa® simulators. You have the freedom to build your testbench using any of these verification languages: SystemVerilog, e, Verilog, VHDL, or C/C++. Simulation VIP supports the Universal Verification Methodology (UVM) as well as legacy methodologies.
- Industry's first UniPro VIP
- Part of the broadest line of MIPI simulation VIP
- has been a MIPI Alliance Contributing Member since 2007
- The UniPro VIP supports MIPI UniPro specification, version 1.41 and version 1.6.
- Enables Master and Slave Design-Under-Test Configurations
- Provides Full Stack and Controller Only verification
- Includes Test Suite
- The user can set the VIP as active or passive without changing the testbench, and determine, during run time, which instance to instantiate.
- Supports both MIPI UniPro 1.6 and 1.41 specification.
- Supports Serial and RMMI interfaces (downstream).
- Supports CPort signal interface (upstream).
Video Demo of the MIPI UniPro Verification IP (VIP)
MIPI UniPro VIP Demo