ONFi (Open Nand Flash Interface) provides an smart way to verify the ONFi host controller or ONFI Flash memory model of a SOC or a ASIC. The SmartDV's ONFi is fully compliant with standard ONFi Specification and provides the following features.
ONFi is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA and non-standard verification env
- Fully compliant to the ONFi 2.1
- Supports Source Synchronous & Asynchronous Mode of operations for individual Target Flash with all timing modes
- Supports up to 4 Target NAND Flash Device with unlimited LOGICAL UNIT, BLOCK & PAGE
- Supports parallel command operation on dual bus.
- Supports Interleaving READ Command Operations
- Supports Multiple LUN Operations
- Supports 16 bit bus width operations
- Supports Interleaving Command operations
- Supports Partial Page Program Operations
- Supports Clock stop feature during Source Synchronous mode of operations
- Device Defective Operation sequence for each Target NAND Flash Device
- Supports Data Pause between Read/Program Operations
- Supports Small Data Move command Operations
- Supports Change ROW Address Command Operations
- Ability to generate Vendor Specific Commands
- Supports Callbacks, so that user can access the data observed by monitor
- Faster testbench development and more complete verification of ONFi designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
- Complete SystemVerilog source code of ONFi.
- Examples's showing how to connect and usage of Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.