Microwire Serial Interface is the serial synchronous communication protocol developed by National Semiconductor. Microwire Serial Interface VIP can be used to verify Master or Slave device following the Microwire Serial Interface basic protocol as defined . It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.
Microwire Serial Interface VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
- Supports configurable address width from 2 to 32bit
- Supports configurable data width from 2 to 64bit
- Support Master and Slave Mode
- Supports 3-wire interface
- Support baud rate selection
- Support internal clock division check.
- Support single and burst transfer mode.
- Support on the fly generation of data.
- Support Failchild, Microchip, Onsemi, ST EEPROM using microwire.
- Built in functional coverage analysis..
- Supports Callbacks in master, slave and monitor for modifying, and sampling data/cmd on Microwire bus.
- Faster testbench development and more complete verification of Microwire
- Serial Interface designs.
- Easy to use command interface simplifies testbench control and configuration of slave and master.
- Simplifies results analysis.
- Runs in every major simulation environment.
- Complete source code of Microwire Serial Interface master, slave and monitor.
- Complete regression suite containing all the Microwire Serial Interface testcases.
- Examples's showing how to connect various components, and usage of Master, Slave and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation contains User's Guide and Release notes.
Block Diagram of the OVM/UVM Microwire Serial Interface VIP