The DesignWare® PCIe Monitor tracks LTSSM states and PCIe transactions at the link, and generates log files and coverage reports which can be used to track verification progress. The log file provides a record of the link activity and shows transactions and the time at which they occurred. The functional coverage report shows coverage versus PCIe Transaction Layer Packets and Data Link Layer Packets. The compliance coverage report shows coverage versus the PCIe compliance checklist. The monitor also allows user definable coverage groups. The Design PCI Express® verification IP is available stand-alone and is included in the DesignWare Library and the VCS Verification Library.
- Configurable for root complex or end point coverage
- Includes protocol-based scenario generation
- Provides coverage of PCI Express compliance checklist
- Provides functional coverage of PCIe packet types
- Generates log files
- Configurable for use at PIPE or 10b interface