Cadence® VIP for PCI Express protocols is a proven solution supporting all major logic simulators and the industry-standard Universal Verification Methodology (UVM).
Cadence VIP for PCI Express protocols provides support for PCI Express specification versions 1.0a, 1.1, 2.0, 2.1, and 3.0, as well as Address Translation Services (ATS), Single-Root I/O Virtualization (SR-IOV), and Multi-Root I/O Virtualization (MR-IOV) protocols. The VIP also supports verification of Mobile PCI Express (M-PCIe) and NVM Express designs.
Cadence VIP for PCI Express protocols is mature, having verified hundreds of production designs. It supports logic simulation as well as simulation-acceleration making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification.
The optional TripleCheck product provides thousands of test cases to simulate PCI Express traffic and to check for compliance with PCI Express specifications, along with an interactive, graphical analysis of coverage results correlated directly to the protocol specification.
- Complies with PCI Express specification versions 1.0a, 1.1, 2.0, 2.1 and 3.0 including approved ECNs
- Verifies Mobile PCI Express (M-PCIe) designs
- Supports the NVM Express specification
- Provides Single-Root (SR) IOV and Multi-Root (MR) IOV support
- Includes Serial and PIPE 1.0, 2.0, 3.0, and 4.0 interfaces
- Enables verification of PCIe Endpoints, Root Complexes, Switches, and Bridges.
- Provides complete PCIe hierarchy enumeration
- Allows direct access to configuration registers
- TripleCheck option provides compliance test suite including thousands of test sequences
- Complies with the Unified Verification Methodology (UVM)
- Plugs into existing verification environments
- Rapid testbench integration reduces time to first test
- Incorporates expertise acquired through many prior applications
- Accelerates protocol compliance verification
- Proven solution eliminates errors and guesswork
- VIP includes bus functional model, automatic protocol checks, coverage model, multi-language testbench interface.