The PCI/PCI-X Verificatgion IP allows designers to test their design for proper operation and compliance to the PCI Local Bus specification or PCI-X Addendum. The model can be used to quickly create a virtual PCI or PCI-X system around a design. The PCI/PCI-X Verification IP features a complete set of high commands and enables extensive testing to ensure that your design is compliant to the latest PCI and PCI-X specification.
The verification IP includes a bus Master, a bus Slave and a monitor that can be controled from Verilog, VHDL, Vera® or C in all major simulators.
The Verification IP is available to all DesignWare® or DesignWare Verification Library licensees.
- Split transactions
- Error generation (bad data, address parity)
- 64-bit extension
- 64-bit addressing
- User specified limit on number of retries the pcimaster_fx performs
- User specified limit on timeout clocks
- Supports PCI 2.3 and PCI-X 2.0
- Controllable from Verilog, VHDL, Vera
- PCI-X 2.0 ECC, DDR, and QDR.
- All Read/Write transactions