The SATA 3.1 Verification IP is the Industry’s most comprehensive protocol validation solution for predictable verification of SATA designs. SATA 3.1 VIP integrates automatic constrain random stimulus generation, protocol checking and functional coverage within a single extensible component, which incorporates operation in all four layers Command, Transport, Link and Physical Layer which significantly reduces the time and cost of verifying complex SATA 3.1 target system designs.
SATA 3.1 VIP provides a simple yet powerful user interface which drastically reduces the time and effort needed to create a verification environment and verify thoroughly to ensure first time right silicon. User can verify the complex design with few test cases in very short time instead of running multiple directed test cases.
SATA 3.1 VIP is reusable, highly configurable, pre-verified, plug and play verification component developed in SystemVerilog solution for SoC incorporating SATA Port for Device / Host at Module, Chip and System level.
- Compliant to SATA 3.1 Specification and UNH-IOL
- Backward Compatible to SATA 1.0 and SATA2.0 specification
- Supports complete Command, Transport, Link and PHY(Logical) Layer
- Support for asynchronous signal recovery
- Support PHY initialization
- Support fully configurable Register, Data and DMA
- Support for CONTp primitive generation and Detection
- Supports Queuing Commands Native & Tagged
- Supports PIPE interface for SATA
- Supports variety of Error Injection at all Layers via callbacks.
- Support Power management (Partial and Slumber States)
- SystemVerilog Source Code
- User Guide and Release Notes
- Sanity Testcases
- Coverage Plan [Upon Request]
- Examples on topological usage
- Sample Verification Environment
Block Diagram of the SATA 3.1 Verification IP