The Synopsys Serial ATA (SATA) VIP is designed to verify SATA-based designs using both random and directed simulation.
The SATA VIP supports constrained random methdologies and and parameterized constrained randomization throughout the layers to aid in achieving coverage during verification.
The SATA VIP is verification methodology neutral, and can be integrated with and controlled by any hardwre verification language such as SystemVerilog including UVM, C/C++, or Verilog)
The SATA VIP supports all popular simulators.
Supports Protocol Analyzer
- SATA Gen 1,2, and 3 plus extensions
- Supports all SATA commands (PIO, DMA, LCQ, NCQ, Send/Receive FPDMA Queued)
- Can be used at any link speed including 6 Gb
- Support for interrupt aggregation
- OOB sequence generation and checking
- Scalable for multiple instantiations in a test bench (for testing multi-port hosts)
- Configurable pattern generation for random, directed or erroneous patterns
- Support for power management modes (Partial, Slumber, Devslp)
- High Performance
- Extensive Protocol verification