The Serial SCSI (SAS) Verification IP is designed to thoroughly verify your design using both random and directed simulation.
The Synopsys SAS VIP provides full SAS functionality and includes application layers that vastly simplify testbench development. Application layers provide simple APIs to generate SAS traffic: a SCSI application layer, an STP SATA Host Exerciser and Management application layer.
The SAS VIP supports paramaterized constrained randomization throughout the layers to aid in coverage during testing.
The SVC is implemented to be verification methodology neutral, and can be integrated with and controlled
by any hardware verification language such as SystemVerilog (including UVM), C/C++, or Verilog.
The VIP runs on all popularsimulators.
- Supports all speeds up to 12 Gb
- OOB sequence generation and checking
- Supports speed negotiation, training, and multiplexing at any link speed
- SCSI Application level exerciser for both unit and system level testing
- Optional STP support with ATA Application level exerciser
- Checkers verify protocol timing checks and functional accuracy at each layer
- Configurable pattern generation for random, directed or erroneous patterns
- Built-in error injection
- Statistics reported at each level to help determine corner case coverage
- High Performance
- Extensive Protocol verification