The USB 2.0 xHCI Verification IP provides an
effective & efficient way to verify the components
interfacing with USB 2.0 protocol layer interface of
an ASIC/FPGA or SoC
The USB 2.0 xHCI VIP is fully compliant with
xHCI standard. This VIP is a light weight VIP with
easy plug-and-play interface so that there is no hit
on the design time and the simulation time.
- USB 2.0 can be handled along with USB 3.
- High speed, Full speed, Low speed are supported.
- Supports all USB transfers.
- Supports all the standard USB requests.
- Compliant with Token, DATA, ACK based protocol.
- xHCI capability registers for USB2.0 are supported.
- Compliant with TD based DMA.
- Supports all kind of TRBs available in xHCI specification.
- Supports LPM.
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
- Unique development methodology to ensure highest levels of quality
- Availability of Compliance & Regression TestSuites
- 24X5 customer support
- Unique and customizable licensing models
- Exhaustive set of assertions and cover points with connectivity example for all the components
- Consistency of interface, installation, operation and documentation across all our VIPs
- Supports wide variety of Dynamic as well as Static Error Injection scenarios
- Supports Callback / User Configuration in Monitor and BFMs
- USB 2.0 xHCIAgent
- USB 2.0 Protocol Monitor
- Test Environment & Test Suite :
- Basic Protocol Tests
- Directed & Random Tests
- Assertions & Coverage Point Tests
- Error Injection Tests
- Protocol Conformance Tests
- Integration Guide, User Manual and Release Notes
Block Diagram of the USB 2.0 xHCI Verification IP Verification IP