Cadence provides mature and comprehensive verification IP (VIP) for USB protocols. Our VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM). Incorporating the latest protocol updates, our USB VIP provides a complete bus functional model with integrated automatic protocol checks, a coverage model for collecting simulation results, and an extensive library of compliance tests. Designed for easy integration in testbenches at IP, SoC, and system levels, Cadence® VIP for USB protocols helps engineers reduce time to first test, accelerate verification closure, and ensure end-product quality.
Features
- Full timing bus functional modeling of the USB 3.0 specification
- Verifies host, device, and hub designs
- Supports OTG 3.0 operation
- Operates in SuperSpeed mode
- Supports backward-compatibility with USB 2.0 in high- and full-speed modes
- Provides full stack verification as well as PIPE-MAC and PIPE-PHY verification
- Provides full power management support
- Simplifies protocol compliance verification via automated stimulus generation and coverage reporting
- Monitors, checks, and collects coverage on bus traffic using automatic protocol checks, including configuration and runtime checks
- Provides a complete USB protocol hierarchy enumeration process
- Provides access to and control of callbacks, packets, and memory mapped registers
- Supports bulk, control, interrupt, and isochronous transfers and bulk streaming protocol
- Supports all engineering change notices (ECNs) to specification
- Enables error injection at each layer
- Handles system-level errors including error detection, reporting, and logging
- Optional SuperSpeed InterChip (SSIC) VIP features include:
- Support for x1, x2, and x4 lane configu- rations
- Supports serial physical interface
- HS-G1, HS-G2, and HS-G3 bursts with data rate series A/B
- LS mode support with PWM-G1 burst
- Provides access to M-TX and M-RX capabilities and attributes through memory-mapped registers
- Supports all M-PHY states as per SSIC specification (SLEEP, STALL, HIBERN8, HS-BURST, PWM-BURST, etc.)
- Optional PureSuite compliance solution features include:
- Supports USB 2.0 and USB 3.0 host, device, and PHY verification
- Tests all protocol layers and key state machines
- Includes verification plan for measuring verification progress
- Built-in functional coverage
- Extensive set of pre-built tests for exercising the design under test
- Error recovery testing
- Tests configurable based on implemen- tation of design under test
- Supports all major simulators
Benefits
- Plugs into existing verification environments
- Rapid testbench integration reduces time to first test
- Incorporates expertise acquired through many prior applications
- Accelerates protocol compliance verification
- Proven solution eliminates errors and guesswork
Deliverables
- VIP includes bus functional model, automatic protocol checks, coverage model, multi-language testbench interface.
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