The USB Power Delivery Specification is expected to make life easier for millions of end consumers by providing a flexible and veratile power delivery mechanism for charging and operating mobile devices. Combined with the ubiquity of the USB port on all kinds of consumer devices (and increasingly even on wall power panels) the USB Power Delivery capability promises to be a mini revolution.
The USB Power Delivery Verification IP de-risks your design IP development effort by providing a high degree of confidence over various design features and scenarios such as Power-up, Hard and Soft Reset, Power Negotiation, Role Swap, GoToMin, Dead Battery, etc. before shipping silicon.
The USB Power Delivery Verfication IP is a comprehensive solution for simulation verification of your USB Power Delivery implementation. The USB Power Delivery Verification IP provides a BFM along with a full-featured constrained-random Test-bench that implements a comprehensive test-plan and coverage suite.
The USB Power Delivery Verification IP Solution works with IP, SOC as well as system level verification environments.
- Conforms to USB Power Delivery Specification version 1.1
- Native SystemVerilog Implementation
- UVM Compliant
- Provides full compliance test-suite
- Provides constrained random test-suite
- Provides coverage suite
- Simulator Support: Synopsys VCS, Mentor Graphics Questa
- Methodology Support: UVM, OVM, VMM
- Supports testing of Producer, Consumer as well as Producer/Consumer and Consumer/Producer
- Supports all Power-up and Hard/Soft Reset cases
- Supports all Power Negotation cases
- Supports all Role Swap cases
- Supports Dead Battery testing
- Supports GoToMin
- Supports BIST
- Supports Error Injection cases
- Supports different power profiles
- Supports modeling some part of implementation in firmware
- Plug-n-Play Verification
- De-risk your design development
- Test Bench
- Test Suite (Directed and Constrained Random)
- Coverage Suite
- User Guide
Block Diagram of the USB Power Delivery Verification IP - Full test bench with BFM and directed and constrained random test suites