On-Demand Webinar
Design and Reuse -The impossible dream?

With the downturn in the global economy, companies must seek ways to improve time-to-market by decreasing design time. By outsourcing critical IP, SoC designers can accomplish this goal. But there must be collaboration between the IP vendor and the customer, especially if IP reuse is to be achieved. Both must understand the needs of the other whether they're economic or technologic. This panel will take a fresh look at design and reuse from a business and technology perspective. Topics covered will include:

- Why outsource in the first place? What are the advantages?
- What degree of collaboration is needed between the IP vendor and customer?
- Do standards solve design compatibility issues, or do they create them?
- What are the design considerations for integrating IP cores when hundreds of cores are involved?
- Tools for design. What is the responsibility of the IP vendor to provide them? Are third party tools adequate?
- License fees or royalties; the pros and cons of each from the vendor and customer perspective
- Building a successful IP business; what does the future hold?

Chairperson:

		Jack Browne Senior Vice President, Sales and Marketing Sonics
	Jack Browne is Sonics’ senior vice president of sales and marketing. Prior to joining Sonics, Mr. Browne served in several executive roles at MIPS Technologies, including executive vice president of worldwide sales and executive vice president of marketing. Earlier in his career, he was the head of Motorola’s 68000 processor marketing team. An acknowledged industry spokesman, Mr. Browne has written more than 100 papers for industry publications and presented at more than 100 industry conferences. He holds a B.S.E.E. degree from the University of Texas.

Panelists:

		Arthur Marris Cadence Design Systems
	Arthur Marris is in charge of Cadence’s synthesizable silicon IP. Mr Marris has been with Cadence since 1998 during which time he has delivered design services and developed soft IP. He has a particular interest in Ethernet technology. Prior to joining Cadence he worked for Texas Instruments for 14 years as a chip designer. He holds an M.Sc. degree from the University of Edinburgh.
		James Aldis Texas Instruments
	James Aldis is an SoC Architect with Texas Instruments' Wireless Terminals Business Unit. His responsibilities include OMAP interconnect and on-chip networking, and chip-level performance modeling for multimedia and mobile computing applications. He has a PhD in coding and modulation from the University of York. Dr. Aldis is vice chairman of the OSCI Transaction-Level-Design Working Group and a Director of the OCP-IP.
		Stefano Ravaglia SoC R&D Director, Computer System Division STMicroelectronics
	Stefano Ravaglia has spent 25+ years designing or managing ASIC/SoC design. He has a Masters in Nuclear Engineering from Politecnico of Milan. He worked for two years at Politecnico. He also worked 10 years for Italtel and another 10 years for LSI Logic (Director of European DC). For the past three years, he’s been at STMicroelectronics as SoC R&D director for the Computer System Division. Main product Custom SoC and Spear™, technology used from 2 um down to 40 nm mainly in telecom, networking and computer.