On-Demand Webinar
Debug and optimisation of embedded software & SoC designs: can scalable on-chip system visibility be delivered cost-effectively?

Embedded software quality and platform optimisation are key to consumer products’ success and differentiation. To deliver such optimised products embedded software and hardware engineers require real-time visibility on how the embedded software and hardware interact, both during the product development cycle and in the final products for new applications, maintenance or failure analysis.
In price sensitive, consumer markets this must be achieved with minimal increase in engineering or unit manufacturing costs.
In this panel, industry leaders in embedded software and hardware development (OEMs, silicon suppliers, IP providers and tool vendors) will analyse market requirements and will debate on how cost effective on-chip visibility can be provided to all the SoC developers and users.

Chairperson:

Michael Dimelow Director of Marketing, Processor Division ARM

Panelists:

		Rolf Kuehnis Nokia
	Rolf Kuehnis is a Senior Technology Manager at Nokia, based in Tampere, Finland. He focuses on debug and trace technologies needed for the development of wireless handsets and is involved in different standardization activities such as MIPI (www.mipi.org) and IEEE 1149.7. Mr. Kuehnis holds a M.Sc. in EE from the Swiss Federal Institute of Technology in Zurich (ETH).
		Gary Swoboda Texas Instrument
	Gary is the Architecture CTO of TI’s debug architectures. His responsibilities involve defining TI s debug technology infrastructure, helping define TI’s overall development tools roadmaps, and influencing the definition of new DSP architectures. He also represents TI in several debug related standards bodies. In 2001, Gary was elected to TI Fellow in recognition of his work on TI debug technology. Gary began his career with TI’s Equipment Group in 1971 after receiving his Bachelor of Science degree at the University of Texas at Austin. Here he gathered systems expertise while working on wide array of high performance computing, telecommunications, radar, and secret military programs. He also worked for an extended period on the Advanced Scientific Computer program, TI’s version of a supercomputer. After moving to TI semiconductor group in 1984, he has architected three generations of TI debug technologies. His work has been instrumental in establishing TI applications debug leadership with these firsts: fully integrated on-chip emulation, PC based toolset, scan based emulation products, JTAG scan based emulation products, and DSP Trace solution. Gary hold over 140 US and Foreign Patents covering System Architecture and Debug Technology, is the Principle Architect and Author for the IEEE P1149.7™ Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture
		Serge Poublan Product Marketing Manager, CoreSight Program Manager ARM
	Serge is a product marketing manager at ARM. He has several product line responsibilities and he is currently in charge of the CoreSight debug and real-time trace IP product portfolio. Within his professional career, Serge hold diverse engineering, program management and marketing roles in the aeronautical, telecom and semiconductor industry; electronics engineer by training he contributed technically and program managed several large scale IP and ASIC developments. Serge is a chartered French electronics engineer and holds an executive diploma in management.
		Stephan Lauterbach Lauterbach
	Stephan is General Manager at Lauterbach, responsible for Debug & Trace tools development. As a co-founder of Lauterbach he has a deep knowledge of debug technology ranging from classic In-Circuit Emulation systems of the past to complex Multicore SoC debug and trace architectures of today. He is a member of MIPI Test&Debug and also involved in other industry organisations.