On-Demand Webinar
Total IP Solutions for Enabling Technology Adoption

SoC's of today are really systems and hence require many more components besides RTL IPs. The panel will discuss synthesizable RTL, verification IPs, analog IPs, software stacks, hardware platforms and tools required for a successful SoC design. The panelists will provide a vendor's perspective as well as a designer's perspective on the importance of total IP solutions required to enable technology adoption.

Chairperson:

		Paul Dempsey Editor-in-Chief EDA Tech Forum Journal
	Paul Dempsey is Editor-in-Chief of EDA Tech Forum Journal and a senior US correspondent for E&T, the magazine published by the Institution of Engineering & Technology. He has been working in the technology sector for almost 20 years, contributing to publications such as EETimes, Red Herring, and specialist newsletters published by the Financial Times.

Panelists:

		Ram Gopalan Senior Director of Marketing Arasan Chip Systems
	Ram Gopalan a 25 year veteran of the semiconductor industry comes with experience at companies like IBM Microelectronics, National Semiconductor and also as a semiconductor entrepreneur at Cognigine. He advises many early stage like Arasan Chip Systems on their marketing strategy and business development and helping them grow. He holds a BS from IIT/Delhi, a MS for UNB, Canada and an exec MBA from Stanford.
		Arthur Marris Staff Design Engineer Cadence Design Systems Inc.
	Arthur Marris is in charge of Cadence’s synthesizable silicon IP. Mr Marris has been with Cadence since 1998 during which time he has delivered design services and developed soft IP. He has a particular interest in Ethernet technology. Prior to joining Cadence he worked for Texas Instruments for 14 years as a chip designer. He holds an M.Sc. degree from the University of Edinburgh.
		Andre Picco ST Ericsson
	Andre Picco leads the High Speed Link team in STEricsson; He has a tremendous 30-year experience in the Design and Validation in several fields of microelectronic including Digital Signal Processor, Super Computer CPU, Design Reuse, microcontroller, Digital TV and High Speed Links. His main focus today is to deliver the HS Link as a full subsystem ( from Interconnect to PADS , associated with Low Level Drivers) validated and ready to use at SOC level. Andre is graduated from Ecole Superieure d’Electricité.
		Atul Bhatia President & CEO nSys Design Systems
	Atul Bhatia founded nSys Design Systems in 2000 after a 20 year career in the semiconductor industry in various technical and business capacities. nSys Verification Suite (nVS) family is the largest collection of Verification IPs available from a single source. Hundreds of ASIC, FPGA & IP developers are currently using the nVS family to benefit from widely accepted & proven BFM, Monitor, Assertions based Checkers and Test Suites. The nVS family is available in native SystemVerilog (OVM/VMM) & Verilog with option of Compliance Test Suites.
		Ignatius Bezzam Senior Director of Engineering Arasan Chip Systems
	With more than 25 years of experience, semiconductor-industry veteran Ignatius Bezzam is Senior Director of Engineering at Arasan Chip Systems. Mr. Bezzam leads the development of deep sub-micron, system-on-chip (SoC) analog and mixed signal intellectual properties (IP) solutions. He is responsible for oversight of global development teams and support of the increasing number of Arasan's worldwide customers in the mobile, PC, consumer electronics and communications markets. Mr. Bezzam most recently served as Director of IC Design at Altierre, Inc., a system house for digital retail solutions. Prior to this he held management and leadership positions at National Semiconductor, Volterra Semiconductor, Maxim Integrated Products, Integrated Circuit Systems and Raytheon Semiconductor. Mr. Bezzam holds a MSEE from San Jose State University and a Bachelor’s degree from IIT Madras. He holds several patents in AMS and PLL IC design and publications in ISSCC and ESSCIRC.