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		<title>Design And Reuse</title>
		<link>http://www.design-reuse.com/</link>
		<description>The industry source for engineers and technical managers worldwide.</description>
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		<copyright>Copyright 2005, Design And Reuse S.A.</copyright>
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			<title><![CDATA[A Step By Step Methodical Approach for Efficient Mixed-Language IP Integration]]></title>
			<link>http://www.design-reuse.com/go2/322996/1</link>
			<description><![CDATA[This paper looks at mixed-language design integration from both the EDA tool developers’ and designers’ perspectives. It describes different approaches and provides useful insights to help users select the best option for integrating two IP blocks in a mixed-language environment. We will provide practical examples based on real designs]]></description>
			<pubDate>Mon, 22 Mar 2010 13:30:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[Rapid Bridge Acquires QThink IC Design]]></title>
			<link>http://www.design-reuse.com/go2/422995/1</link>
			<description><![CDATA[Rapid Bridge announced today that it has made an asset purchase of QuantumThink Group, a San Diego-based, privately-held IC design services company with offices in San Jose and Bangalore, India. The acquisition will enable Rapid Bridge to offer its clients full front-to-back IC design services.]]></description>
			<pubDate>Mon, 22 Mar 2010 13:15:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Vitesse's New Forward Error Correction Technology Accelerates Migration to 100G]]></title>
			<link>http://www.design-reuse.com/go2/422994/1</link>
			<description><![CDATA[Vitesse today announced immediate availability of its enhanced forward error correction (eFEC) technology for implementation in ASICs or FPGAs. Vitesse's new, patented Continuously Interleaved BCH (CI-BCH™) eFEC code offers the highest performing hard decision eFEC available today and is the industry’s only eFEC implementable in single FPGA form at 100G. ]]></description>
			<pubDate>Mon, 22 Mar 2010 13:03:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Mindspeed Achieves LTE Standards Compliance for Transcede Reference Software Using Agilent Technologies' SystemVue Environment ]]></title>
			<link>http://www.design-reuse.com/go2/422990/1</link>
			<description><![CDATA[Mindspeed today announced that the company’s reference software for its recently introduced Transcede™ baseband processor has been verified for compliance with the latest long-term evolution (LTE) Layer 1 standard 3rd Generation Partnership Project (3GPP) TS 36.141. ]]></description>
			<pubDate>Mon, 22 Mar 2010 11:56:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Stereo 20-bit 48kSps ADC from Alvand Technologies, Inc]]></title>
			<link>http://www.design-reuse.com/go2/122989/1</link>
			<description><![CDATA[Stereo 20-bit 48kSps ADC from Alvand Technologies, Inc]]></description>
			<pubDate>Mon, 22 Mar 2010 11:45:00 GMT</pubDate>
			<category domain="">New Products</category>
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			<title><![CDATA[Semiconductor Industry 2025 (Silicon Valley Blog - Daniel Nenni)]]></title>
			<link>http://www.design-reuse.com/go2/722987/1</link>
			<description><![CDATA[Per my previous blogs, mobile internet devices are a leading driver of semiconductor growth. Next-generation semiconductors will enable new mobile applications that take advantage of high-speed data connections, high-performance applications, added processing capabilities, and long battery lifetime. The result being exploding data usage and a 3G wireless bottleneck.]]></description>
			<pubDate>Mon, 22 Mar 2010 11:36:00 GMT</pubDate>
			<category domain="">Industry Expert Blogs</category>
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			<title><![CDATA[Is Outsourcing Dying or Thriving? (Part 3) (Entrepreneur Journeys - Sramana Mitra)]]></title>
			<link>http://www.design-reuse.com/go2/722988/1</link>
			<description><![CDATA[In part I of my article, I pointed out the reasons why outsourcing to India based on pure labor rate arbitrage faces significant obstacles to continued growth – and possibly even to future survival. On the other hand, outsourcing is clearly thriving – in India and around the world. How can we reconcile this?]]></description>
			<pubDate>Mon, 22 Mar 2010 08:39:00 GMT</pubDate>
			<category domain="">Industry Expert Blogs</category>
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			<title><![CDATA[Multiple Tensilica IP Cores Power NEC, Fujitsu and Panasonic Mobile Communications Fully Functional LTE Handset SOC for Major Japanese Wireless Carrier]]></title>
			<link>http://www.design-reuse.com/go2/422986/1</link>
			<description><![CDATA[Tensilica today announced that NTT DOCOMO has confirmed that several Tensilica Xtensa LX dataplane processor cores (DPUs) are used in the latest LTE mobile handset system-on-chip (SOC) design demonstrated in February at the Mobile World Congress.]]></description>
			<pubDate>Mon, 22 Mar 2010 05:28:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Intilop (formerly Intelop) corporation's TCP Offload engine IP solution delivers amazing TCP/IP throughput as reported by customers in system level performance testing]]></title>
			<link>http://www.design-reuse.com/go2/422991/1</link>
			<description><![CDATA[This second generation Customizable Full TCP offload Engine also integrates GEMAC, ARP module, RDMA engines, PLB/405 bus interfaces. It is capable of implementing/accelerating hundreds of simultaneous TCP sessions, delivering 800 % -1500% performance improvement over TCP/IP software implementations. ]]></description>
			<pubDate>Mon, 22 Mar 2010 01:30:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Chip market to slow in second half, says TSMC's Chang]]></title>
			<link>http://www.design-reuse.com/go2/422993/1</link>
			<description><![CDATA[TSMC Chairman Morris Chang has said he expects chip market growth to slow in the second half of 2010, before picking up again in 2011, according to a Taiwan Economic News report. ]]></description>
			<pubDate>Fri, 19 Mar 2010 23:45:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Imagination Technologies Group plc - Interim Management Statement]]></title>
			<link>http://www.design-reuse.com/go2/422983/1</link>
			<description><![CDATA[Imagination Technologies is today issuing its Interim Management Statement for the period from 1 November 2009 to 19 March 2010. The Group has continued to see growing and considerable active interest in its technologies across many partners and markets.]]></description>
			<pubDate>Fri, 19 Mar 2010 21:52:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[EDA is not enough! ]]></title>
			<link>http://www.design-reuse.com/go2/322985/1</link>
			<description><![CDATA[Good EDA tools, even combined within well-automated flows, are not enough to produce quality designs, whatever those designs are for software, systems-on-chip (SoCs), integrated circuits (ICs), intellectual property (IP) or embedded systems.]]></description>
			<pubDate>Fri, 19 Mar 2010 21:19:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[Intrinsix to Host New England Semiconductor Council Networking Event April 7th]]></title>
			<link>http://www.design-reuse.com/go2/422982/1</link>
			<description><![CDATA[Intrinsix to Host New England Semiconductor Council Networking Event  with Guest Speaker Norm Armour, VP &amp; GM, Fab 8, Malta, NY, GLOBALFOUNDRIES. ]]></description>
			<pubDate>Fri, 19 Mar 2010 12:29:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Updated: Sequans' WiMax chip drives Sprint Nextel's first 4G phone]]></title>
			<link>http://www.design-reuse.com/go2/422992/1</link>
			<description><![CDATA[It turns out that it's Sequans Communications, not Beceem, whose WiMax chip was designed into Sprint Nextel's first WiMax (4G) phone, scheduled to be unveiled next week during the CTIA wireless show. ]]></description>
			<pubDate>Thu, 18 Mar 2010 23:40:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[LVDS Transmitter from HCL Technologies ]]></title>
			<link>http://www.design-reuse.com/go2/122981/1</link>
			<description><![CDATA[LVDS Transmitter from HCL Technologies ]]></description>
			<pubDate>Thu, 18 Mar 2010 17:32:00 GMT</pubDate>
			<category domain="">New Products</category>
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			<title><![CDATA[24 bit 96dB Dynamic Range 8 to 192kHz Sampling Rate Stereo Audio Codec, UMC 65nm from Synopsys]]></title>
			<link>http://www.design-reuse.com/go2/122980/1</link>
			<description><![CDATA[24 bit 96dB Dynamic Range 8 to 192kHz Sampling Rate Stereo Audio Codec, UMC 65nm from Synopsys]]></description>
			<pubDate>Thu, 18 Mar 2010 17:28:00 GMT</pubDate>
			<category domain="">New Products</category>
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			<title><![CDATA[SPI Serial Flash Controller from ALMA Technologies]]></title>
			<link>http://www.design-reuse.com/go2/122979/1</link>
			<description><![CDATA[SPI Serial Flash Controller from ALMA Technologies]]></description>
			<pubDate>Thu, 18 Mar 2010 17:18:00 GMT</pubDate>
			<category domain="">New Products</category>
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			<title><![CDATA[Implementing custom DDR and DDR2 SDRAM external memory interfaces in FPGAs (part 1) ]]></title>
			<link>http://www.design-reuse.com/go2/322977/1</link>
			<description><![CDATA[This is a two-part article that focuses on the design guidelines and describes how to implement DDR or DDR2 external memory interfaces (EMIFs) using FPGAs via ALTDLL and ALTDQ_DQS megafunctions.]]></description>
			<pubDate>Thu, 18 Mar 2010 16:40:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[Lessons for IP reuse]]></title>
			<link>http://www.design-reuse.com/go2/422974/1</link>
			<description><![CDATA[In the ten years or so that it has taken for design reuse, or design with IP, to go from a niche interest to mainstream chip implementation, teams have developed an understanding of what it can do for them, and how to budget accordingly. However, there are still surprises to be negotiated, as some aspects of design reuse are counter-intuitive, especially when it comes to reusing some piece of IP developed in-house in another chip. Designers ]]></description>
			<pubDate>Thu, 18 Mar 2010 14:55:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Synopsys Likely To Roll-Up The EDA Sector (Entrepreneur Journeys - Sramana Mitra)]]></title>
			<link>http://www.design-reuse.com/go2/722973/1</link>
			<description><![CDATA[Analysts are projecting positive trends for the electronics industry in the current year, with estimates ranging from 7% to 9% annual growth. Also, investment in R&amp;amp;D is expected to return after slowing last year. The increased demand is expected to drive growth in the semiconductor industry. Conservative estimates predict 2010 to be a year of stabilization for the EDA space followed by growth in 2011, and 2010 is expected to be a year of industry consolidation. The largest player, Synopsys (NASDAQ:SNPS), is already acquiring smaller players in the market and will continue to do so. Cadence is trading at half of Synopsys’ market cap, which makes their acquisition currency weaker. Let’s take a look at the last quarter’s happenings.]]></description>
			<pubDate>Thu, 18 Mar 2010 14:21:00 GMT</pubDate>
			<category domain="">Industry Expert Blogs</category>
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			<title><![CDATA[Currently profitable global semicon industry needs to remember lessons of downturn! (Pradeep's Point! - Pradeep Chakraborty)]]></title>
			<link>http://www.design-reuse.com/go2/722972/1</link>
			<description><![CDATA[Early this week, iSuppli reported that the global semiconductor industry is currently at its ‘most profitable level in a decade.’ So, I asked iSuppli whether it was too early to call the semicon industry most profitable, given that we’ve survived the worst downturn and the fact that lot of capacities are being built up? However, this is indeed a noteworthy performance.  According to iSuppli, ‘The overall semiconductor supplier operating profitability rose to 21.4 percent in fourth quarter of 2009, the highest level since the fourth quarter of 2000 when it reached 24.7 percent. Industry profitability soared in 2009, rising throughout the year after falling to negative 5.3 percent in the first quarter due to the impact of the global economic downturn.’]]></description>
			<pubDate>Thu, 18 Mar 2010 14:15:00 GMT</pubDate>
			<category domain="">Industry Expert Blogs</category>
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			<title><![CDATA[Energy Micro finally takes venture funding (Shrinking Violence Blog - Chris Edwards )]]></title>
			<link>http://www.design-reuse.com/go2/722971/1</link>
			<description><![CDATA[Geir Førre, founder and CEO of low-power microcontroller startup Energy Micro was in no hurry to raise venture funding for his company. Having sold his previous startup Chipcon to Texas Instruments, he was able to use his own money to get Energy Micro off the ground for around. And with some money from the Norwegian government and lead customers, the company had $6m to get to its first product launch, the EFM32 Gecko that appeared last year. It took $3m, according to Førre, to get the Gecko out of the door and employ, as of October, around 30 people. The remainder was seen as enough to get the company to the middle of this year and has since taken on some more people, taking its headcount to 35. To get further, the company has raised $13m in venture funding. Last year, Førre said Energy Micro was looking for around $10m, arguing that it need not take much to get a fabless startup off the ground and into revenue.]]></description>
			<pubDate>Thu, 18 Mar 2010 14:12:00 GMT</pubDate>
			<category domain="">Industry Expert Blogs</category>
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			<title><![CDATA[Arteris Announces Support For New ARM AMBA 4 Interconnect Specification]]></title>
			<link>http://www.design-reuse.com/go2/422970/1</link>
			<description><![CDATA[Arteris today announced support for the new ARM(R) AMBA(R) 4 specification. Arteris and ARM are working together to ensure interoperability between the AMBA 4 AXI(TM) 4 interface protocol and the Arteris Network on Chip (NoC), and are partnering to deliver optimal system performance for SoC designers using AXI4 protocol-compliant IP together with Arteris NoC interconnect technology.]]></description>
			<pubDate>Thu, 18 Mar 2010 12:32:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[12-bit 160MSPS Dual D/A Converter,  Silicon Proven in TSMC 40nm from Cosmic Circuits]]></title>
			<link>http://www.design-reuse.com/go2/122969/1</link>
			<description><![CDATA[12-bit 160MSPS Dual D/A Converter,  Silicon Proven in TSMC 40nm from Cosmic Circuits]]></description>
			<pubDate>Thu, 18 Mar 2010 10:03:00 GMT</pubDate>
			<category domain="">New Products</category>
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			<title><![CDATA[Motor Control IC vs Motor Control IP (FPGA Technology in Power Electronics Applications - Marc Perron)]]></title>
			<link>http://www.design-reuse.com/go2/722976/1</link>
			<description><![CDATA[System level design is in the air. This is also true for motor control applications. Up to now, this blog has mainly focused on commenting third-party articles relating to FPGA as a&amp;nbsp;chip for embedded system development in power electronics applications, mostly for motor control. Unfortunately, most of those third-party&amp;nbsp;articles have&amp;nbsp;been written with an&amp;nbsp;”old”&amp;nbsp;chip thinking&amp;nbsp;comparing FPGA solely as another alternative to COTS DSP and MCUs. From a certain point of view this is completely understandable: those&amp;nbsp;articles have been written by motor control people who have been using DSP since the last 15 years.&amp;nbsp;Since the 90s, digital motor control embedded system design&amp;nbsp;has been&amp;nbsp;roughly the following: buy a DSP chip + plug it with other&amp;nbsp;components on a PCB + program&amp;nbsp;the DSP + plug your motor&amp;nbsp;and check how is the motor running. Why it shouldn’t be the same with FPGAs in 2010&amp;nbsp;?]]></description>
			<pubDate>Thu, 18 Mar 2010 03:42:00 GMT</pubDate>
			<category domain="">Industry Expert Blogs</category>
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			<title><![CDATA[Who is largest buyer of chips?]]></title>
			<link>http://www.design-reuse.com/go2/422975/1</link>
			<description><![CDATA[Who is the largest buyer of chips?]]></description>
			<pubDate>Thu, 18 Mar 2010 02:20:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Analyst: Tabula won't have immediate market impact]]></title>
			<link>http://www.design-reuse.com/go2/422978/1</link>
			<description><![CDATA[Programmable logic startup Tabula turned some heads with the announcement earlier this month of its novel architecture and introduction of its first products this week. But the company poses no immediate threat to the dominance of market leaders Xilinx and Altera, according to a Wall Street analyst. ]]></description>
			<pubDate>Thu, 18 Mar 2010 02:15:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[MIPS Technologies and DMP Collaborate on Android(TM) Development for MIPS(R) Architecture]]></title>
			<link>http://www.design-reuse.com/go2/422968/1</link>
			<description><![CDATA[MIPS and DMP today announced that DMP has become a member of the MIPS Alliance Program for its Android™ on MIPS initiative. The alliance will ultimately enable SoC developers to create MIPS-Based™ SoCs with DMP PICA/SMAPH series graphics IP cores. ]]></description>
			<pubDate>Wed, 17 Mar 2010 21:41:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[ViaSat Announces New 100G Optical Transport Forward Error Correction (FEC) Products and Digital Signal Processing Services]]></title>
			<link>http://www.design-reuse.com/go2/422967/1</link>
			<description><![CDATA[ViaSat is introducing a family of forward error correction (FEC) products for 100G optical transport. These FEC and digital signal processing (DSP) products, available in either FPGA or ASIC cores, can provide major cost savings over optical compensation techniques, increase optical channel capacity, and extend the range of transmission for optical cables.]]></description>
			<pubDate>Wed, 17 Mar 2010 21:19:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Pistols at Dawn: Finding the middle ground between building and assembling (A View from the Top: A System-Level Blog - Frank Schirrmeister)]]></title>
			<link>http://www.design-reuse.com/go2/722966/1</link>
			<description><![CDATA[Being challenged to a duel (see the last paragraph here) can be scary. It often helps to re-visit what one is dueling about. The discussion in question here is about the role of IP reuse vs. high-level synthesis. And as is most life situations the truth probably lies somewhere in the middle, and for sure not in the extreme position   ]]></description>
			<pubDate>Wed, 17 Mar 2010 18:07:00 GMT</pubDate>
			<category domain="">Industry Expert Blogs</category>
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			<title><![CDATA[CoWare Announces Software Development Solution for ARM Cortex-A5 and ARM Cortex-M4 Processor-Based Designs]]></title>
			<link>http://www.design-reuse.com/go2/422965/1</link>
			<description><![CDATA[CoWare today announced support for Fast Models from ARM for Cortex™-A5 and Cortex-M4 processor IP in CoWare’s SystemC-based software development solution. Customers around the world have already successfully deployed CoWare virtual platforms using Fast Models from ARM. ]]></description>
			<pubDate>Wed, 17 Mar 2010 14:03:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Innovative Silicon's Z-RAM Technology Meets Low Voltage and Bulk Silicon Requirements of DRAM Memory Manufacturers]]></title>
			<link>http://www.design-reuse.com/go2/422964/1</link>
			<description><![CDATA[Innovative Silicon today announced two major breakthroughs to its Z-RAM technology. First, bit cell operating voltage has been reduced to below one volt (1V), making it the industry’s lowest-voltage FB memory bit cell and the first to be on-par with traditional DRAM voltages. Second, Z-RAM technology is now constructed on bulk silicon – without the requirement for expensive silicon on insulator (SOI) substrates – by using the 3D transistor structures preferred by the major DRAM manufacturers. ]]></description>
			<pubDate>Wed, 17 Mar 2010 13:54:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[ARM AMBA 4 Protocol And VIP - A Closer Look (Industry Insights Blog - Richard Goering , Cadence)]]></title>
			<link>http://www.design-reuse.com/go2/722963/1</link>
			<description><![CDATA[ARM last week announced the first phase of its AMBA 4 specification, and Cadence simultaneously released Incisive verification IP (VIP) for the e language and SystemVerilog. So why is ARM releasing AMBA 4, what's in the two phases, and what's in the VIP? To get a closer look at what's in the AMBA 4 specification I talked to Keith Clarke, vice president and general manager of Fabric IP at ARM's Processor Division. The widely-used AMBA 3 spec has been around since 2003, and it was time for an upgrade, Keith said. He noted that AMBA 4 was developed in conjunction with some 35 partners, including Cadence. A big motivation, he said, is the increase in performance of processor cores, as well as the ability to place multiple cores on SoCs and to support many different functions on a chip. Additionally, the phase one release that was disclosed last week adds new support for FPGAs. Phase one includes the AXI4, AXI4-Lite, and AXI-Stream protocols. The phase two release, which will be disclosed later this year, will bring in features that will help users develop and program multicore SoCs. Pete Heller, product line manager for VIP at Cadence, said he is &quot;definitely seeing interest&quot; among the customer base for AMBA 4. &quot;The traditional mobile guys are currently planning their roadmaps for it,&quot; Pete said. What's attracting customers, he said, is increased performance, along with a hoped-for power savings. ]]></description>
			<pubDate>Wed, 17 Mar 2010 10:02:00 GMT</pubDate>
			<category domain="">Industry Expert Blogs</category>
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			<title><![CDATA[Aldi Nord, Aldi Sud and Lidl Sued for MPEG-2 Patent Infringement]]></title>
			<link>http://www.design-reuse.com/go2/422962/1</link>
			<description><![CDATA[MPEG LA today announced that several patent holders in MPEG LA’s MPEG-2 Patent Portfolio License have filed separate patent enforcement actions in Landgericht Düsseldorf, Germany against Aldi Nord and Aldi Süd, as well as Lidl Lidl, for infringing patents essential to the MPEG-2 digital video compression standard used worldwide in digital television broadcasting and DVD.]]></description>
			<pubDate>Wed, 17 Mar 2010 09:58:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Actel Corporation Updates First Quarter Guidance]]></title>
			<link>http://www.design-reuse.com/go2/422961/1</link>
			<description><![CDATA[Actel today announced that first quarter 2010 revenues are expected to be up sequentially four percent to eight percent. The previous guidance was up two percent to six percent.]]></description>
			<pubDate>Wed, 17 Mar 2010 09:55:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[NEC Electronics and Renesas Announce the New Organizational Structure and Personnel Changes Following Merger]]></title>
			<link>http://www.design-reuse.com/go2/422958/1</link>
			<description><![CDATA[NEC Electronics and Renesas Technology  today announced the new organizational structure and personnel changes of Renesas Electronics, the new integrated company that will be formed on April 1, 2010 when the business integration of the two entities is completed.]]></description>
			<pubDate>Tue, 16 Mar 2010 14:11:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Party like it's 1999 (Shrinking Violence Blog - Chris Edwards )]]></title>
			<link>http://www.design-reuse.com/go2/722955/1</link>
			<description><![CDATA[Industry analyst firm iSuppli has run the numbers on companies in the semiconductor business and found they are turning in levels of operating profitability not seen since the glory days of the Internet boom. Overall operating profitability rose to 21.4 per cent according to iSuppli in the fourth quarter of 2009, the highest level since the last quarter of 2000. Those working around the industry then will remember those heady days, which were quickly followed by a sudden post-Christmas hangover when purchasing managers staggered into their warehouses and wondered: “Cripes. Did we really order all this stuff?”]]></description>
			<pubDate>Tue, 16 Mar 2010 08:11:00 GMT</pubDate>
			<category domain="">Industry Expert Blogs</category>
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			<title><![CDATA[Gigabit Ethernet Transcoder / OPU0 Mapper from Xelic]]></title>
			<link>http://www.design-reuse.com/go2/122951/1</link>
			<description><![CDATA[Gigabit Ethernet Transcoder / OPU0 Mapper from Xelic]]></description>
			<pubDate>Mon, 15 Mar 2010 16:08:00 GMT</pubDate>
			<category domain="">New Products</category>
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			<title><![CDATA[TSMC 28nm HS/LPT memories, standard cells and GPIO from ChipStart]]></title>
			<link>http://www.design-reuse.com/go2/122949/1</link>
			<description><![CDATA[TSMC 28nm HS/LPT memories, standard cells and GPIO from ChipStart]]></description>
			<pubDate>Mon, 15 Mar 2010 15:48:00 GMT</pubDate>
			<category domain="">New Products</category>
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			<title><![CDATA[Verification of USB 3.0 Device IP Core in Multi-Layer SystemC Verification Environment ]]></title>
			<link>http://www.design-reuse.com/go2/322947/1</link>
			<description><![CDATA[The paper describes the methodology used for functional verification of the USB 3.0 device controller core. The core model has been developed at two different levels of abstraction: RTL model for synthesis and SystemC TLM model for high speed simulation, early software development and early test-bench creation.]]></description>
			<pubDate>Mon, 15 Mar 2010 14:28:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[A Flexible, Field-programmable ROM Replacement]]></title>
			<link>http://www.design-reuse.com/go2/322942/1</link>
			<description><![CDATA[For large amounts of on-chip code and data, mask read-only memory (ROM) provides an inexpensive and easily programmed storage mechanism. However, the inability to configure ROM after wafer processing means that information stored in the ROM cannot be changed in the field. Antifuse one-time programmable (OTP) provides a flexible, field-programmable alternative to ROM. An antifuse-based bit cell uses controlled, irreversible thin (gate) oxide breakdown to program a bit.]]></description>
			<pubDate>Mon, 15 Mar 2010 10:39:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[TSMC Earthquake Damage Redo (Silicon Valley Blog - Daniel Nenni)]]></title>
			<link>http://www.design-reuse.com/go2/722939/1</link>
			<description><![CDATA[As you may know I enjoy poking fun at the current state of semiconductor design and manufacture media; sloppy reporting, editors with little or no actual semiconductor experience taking corporate marketing spins on news/events and passing it along as fact. This time it is the ElectronicsWeakly top viewed article TSMC Loses 40K Wafers In Quake by one of my fellow bloggers David Manners. There was a lot of press on this topic last week but David is the only one to put a number (40,000 wafers, which is significant) on the loss, and he led with it in an article versus his blog (insert sinister music here). The question is: Where did David get a 40,000 wafer loss number?]]></description>
			<pubDate>Mon, 15 Mar 2010 10:05:00 GMT</pubDate>
			<category domain="">Industry Expert Blogs</category>
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			<title><![CDATA[Foundry mix (Shrinking Violence Blog - Chris Edwards )]]></title>
			<link>http://www.design-reuse.com/go2/722937/1</link>
			<description><![CDATA[This is the last time a graph like this will appear for a while. Because Chartered Semiconductor Manufacturing is now part of Globalfoundries there won’t be an opportunity to get information on the processes the company is running from financial reports. AMD will only report profit or loss in its figures now that the company has switched to equity accounting even though AMD holds the lion’s share of the key stock class that determines overall ownership.]]></description>
			<pubDate>Mon, 15 Mar 2010 09:44:00 GMT</pubDate>
			<category domain="">Industry Expert Blogs</category>
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			<title><![CDATA[Is Outsourcing Dying Or Thriving? (Part 2) (Entrepreneur Journeys - Sramana Mitra)]]></title>
			<link>http://www.design-reuse.com/go2/722938/1</link>
			<description><![CDATA[It has now been two years since Sramana Mitra’s article “The Death of Indian Outsourcing” was published. Is outsourcing dying – or thriving? In one sense, outsourcing in India as it was known in the past is on the verge of (and in some cases is already) “hitting the wall.” Pure labor arbitrage-based outsourcing is dependent upon wage rate differentials. While the global economic downturn may have slowed the rate of wage inflation in India, it will return as soon as the world economies return to “normal” – and likely with a vengeance. ]]></description>
			<pubDate>Mon, 15 Mar 2010 05:01:00 GMT</pubDate>
			<category domain="">Industry Expert Blogs</category>
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			<title><![CDATA[Acoustic Echo Canceller from Encore Software]]></title>
			<link>http://www.design-reuse.com/go2/122950/1</link>
			<description><![CDATA[Acoustic Echo Canceller from Encore Software]]></description>
			<pubDate>Mon, 15 Mar 2010 02:59:00 GMT</pubDate>
			<category domain="">New Products</category>
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			<title><![CDATA[Can Tabula and Tier Logic be successful? (Olivier Coudert's Blog - Olivier Coudert)]]></title>
			<link>http://www.design-reuse.com/go2/722930/1</link>
			<description><![CDATA[The past two weeks were pretty interesting if you follow FPGAs. Yes, Xilinx and Altera kept upping their target to Wall St., but that is not where the excitement came from. It came from the recent announcements of two startups, both created in 2003 and heavily funded. Tabula released its long-awaited device, which goes by the sexy name of “Spacetime”. And Tier Logic left its stealth mode this week to announce its own device, “TierFPGA”. The dominant factor in classical FPGA architecture is the interconnect: most of the die area is taken by the wires and the interconnect switches and muxes. If you can somehow reduce the area dedicated to interconnect, you can augment the logic density and lessen the cost of the device. Tabula and Tier Logic pitch a 3D architecture to address the interconnect bottleneck, albeit in very different flavors.]]></description>
			<pubDate>Fri, 12 Mar 2010 14:31:00 GMT</pubDate>
			<category domain="">Industry Expert Blogs</category>
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			<title><![CDATA[Fully configurable N-point FFT/IFFT core from Noesis Technologies]]></title>
			<link>http://www.design-reuse.com/go2/122929/1</link>
			<description><![CDATA[Fully configurable N-point FFT/IFFT core from Noesis Technologies]]></description>
			<pubDate>Fri, 12 Mar 2010 07:36:00 GMT</pubDate>
			<category domain="">New Products</category>
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			<item>
			<title><![CDATA[Configurable Parallel Processing Platform from Silicon Hive]]></title>
			<link>http://www.design-reuse.com/go2/122927/1</link>
			<description><![CDATA[Configurable Parallel Processing Platform from Silicon Hive]]></description>
			<pubDate>Thu, 11 Mar 2010 16:40:00 GMT</pubDate>
			<category domain="">New Products</category>
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			<title><![CDATA[Viewpoint: Your future is programmable]]></title>
			<link>http://www.design-reuse.com/go2/322924/1</link>
			<description><![CDATA[The state of the electronics industry today, and certainly in the future, directly challenges that traditional view of technology-focused product design evolution.]]></description>
			<pubDate>Thu, 11 Mar 2010 15:57:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[TierLogic lifts the veil: another take on the 3D FPGA (Practical Chip Design - Ron Wilson, EDN )]]></title>
			<link>http://www.design-reuse.com/go2/722922/1</link>
			<description><![CDATA[TierLogic, yet another large and expensive FPGA start-up that has been in stealth mode for years, today unveiled a radical approach to increasing the density and utility of large programmable logic devices. Like previously-announced Tabula, TierLogic describes their design as a 3D FPGA. But the two approaches are totally unlike each other, and neither is related to the concept of 3D ICs—involving stacked dice and through-silicon vias—that is currently the hot topic in SoC-of-the-future circles.]]></description>
			<pubDate>Thu, 11 Mar 2010 15:37:00 GMT</pubDate>
			<category domain="">Industry Expert Blogs</category>
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			<title><![CDATA[Challenging Misconceptions About Verification Languages (Industry Insights Blog - Richard Goering , Cadence)]]></title>
			<link>http://www.design-reuse.com/go2/722921/1</link>
			<description><![CDATA[One thing I learned from the recent DVCon conference is that there are a number of common misconceptions about hardware verification languages (HVLs). I had a few of these myself. Two provocative and well-attended presentations provided a different way of looking at HVLs:  &quot;Apples Versus Apples HVL Comparison Finally Arrives.&quot; Presented by Brett Lammers of Cadence Feb. 24.  &quot;Where OOP Falls Short of Verification Needs.&quot; Presented by Matan Vax of Cadence Feb. 25. Some of the misconceptions identified in these talks are as follows.]]></description>
			<pubDate>Thu, 11 Mar 2010 15:32:00 GMT</pubDate>
			<category domain="">Industry Expert Blogs</category>
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			<title><![CDATA[MEMS makes the trip into a CMOS fab (Shrinking Violence Blog - Chris Edwards )]]></title>
			<link>http://www.design-reuse.com/go2/722920/1</link>
			<description><![CDATA[Micromachined chips promise much, which is why every time they turn up in a new system — such as the Nunchuk controller in the Nintendo Wii or the motion sensor in the iPhone — it’s tempting to herald a new dawn for MEMS. It’s invariably a case of “this time it’s all going to happen for MEMS”. But some big problems still face MEMS. It’s not as cheap to make as you’d expect and the one thing you’d expect manufacturers would have down to a fine art — integration with other microelectronics — is still not easy to do. It’s even hard to package the things. They often need to be carefully sealed using special caps to stop moisture disrupting their delicate inner workings. ]]></description>
			<pubDate>Thu, 11 Mar 2010 15:03:00 GMT</pubDate>
			<category domain="">Industry Expert Blogs</category>
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			<title><![CDATA[When Will We Move From RTL to TLM? I Need to Know! (Logic Design - Jack Erickson, Cadence)]]></title>
			<link>http://www.design-reuse.com/go2/722919/1</link>
			<description><![CDATA[My esteemed colleague, Steve Brown, recently wrote a well-thought piece trying to forecast what it will take to move the bulk of design from RTL abstraction to transaction-level modeling (TLM). He uses the gate-level to RTL migration as a reference point so that we can learn from history. He lists a lot of factors that enabled the mainstream shift from gate-level to RTL, and sketches out a similar list of what would be required to move from RTL to TLM. It's a long list. Having worked in the logic design area of EDA since roughly 1993, I'd like to offer my own take. And given that I'm product manager of a product named &quot;RTL Compiler&quot;, I have a personal interest in understanding this.]]></description>
			<pubDate>Mon, 08 Mar 2010 23:01:00 GMT</pubDate>
			<category domain="">Industry Expert Blogs</category>
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			<title><![CDATA[ARM show new AMBA specs: think FPGAs and multicore (Practical Chip Design - Ron Wilson, EDN )]]></title>
			<link>http://www.design-reuse.com/go2/722901/1</link>
			<description><![CDATA[ARM this morning took the wraps off its plans for release of a new silicon interconnect specification: AMBA 4. The company intends to publicly describe AMBA 4 in two phases during this year. IP products implementing the specification will follow later in the year. Director of marketing for fabrics Michael Dimelow explained that evolution in ARM's markets has created requirements for the new spec. One set of driving forces is exemplified by ARM's joint development with Xilinx. The point of that work is not to implement a small ARM core in an FPGA. That's a solved problem. Rather, the work focuses on creating a framework for advanced SoCs—such as Internet-Protocol switch and packet-processor ICs—with substantial ARM CPUs, function-specific accelerators, and large embedded RAMs. Such chips are not small-scale microcontroller-like implementations, nor are they prototypes of ASIC designs. They are in themselves multicore SoCs that attempt to exploit the enormous potential bandwidth of the latest FPGAs.]]></description>
			<pubDate>Mon, 08 Mar 2010 17:15:00 GMT</pubDate>
			<category domain="">Industry Expert Blogs</category>
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			<title><![CDATA[Initial Investigations into UML Based Architectural Reference Patterns for Set-Top Boxes ]]></title>
			<link>http://www.design-reuse.com/go2/322897/1</link>
			<description><![CDATA[This paper analyses a leading-edge Set-top Box (STB) design for architecture reference patterns.  Specifically, the following contributions are made: (i) identifying and documenting (in UML) STB architectural reference patterns, and (ii) providing empirical (quantitative) analysis of pattern use.]]></description>
			<pubDate>Mon, 08 Mar 2010 15:24:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[Selecting an embedded MCU: How to avoid evaluation trap? ]]></title>
			<link>http://www.design-reuse.com/go2/322878/1</link>
			<description><![CDATA[The main goal of this article is to focus on the difficulties encountered by SoC integrators when selecting an embedded microcontroller (MCU). Indeed, the selection is based on MCU performances, but the comparison can be difficult and compromised when considering all the parameters influencing these performances.]]></description>
			<pubDate>Mon, 08 Mar 2010 14:40:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[Decompiling the ARM architecture code]]></title>
			<link>http://www.design-reuse.com/go2/322896/1</link>
			<description><![CDATA[At UBM TechInsights we are often tasked with proving patent infringement of a software algorithm as part of our IP Management Services. Our example algorithm is based on the ARM architecture.]]></description>
			<pubDate>Mon, 08 Mar 2010 14:35:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[Intel Atom, ARM CPU IP, and Embedded World 2010 (Eric Schorn's Processors for People Blog - Eric Shorn)]]></title>
			<link>http://www.design-reuse.com/go2/722888/1</link>
			<description><![CDATA[I am now back from an absolutely exhausting trip to Embedded World 2010 and remain incredibly excited about the ARM Partnership’s prospects in this space. Cortex-M4 is less than two weeks old, fits perfectly alongside the wildly popular Cortex-M3 and Cortex-M0 (the M1 is all about FPGA), &amp;nbsp;and the people I spoke with have grand plans for its future. 5 licensees are already in place, with 2 in the shadows, and you can imagine many more in the future pipeline. On top of that, I spotted a few Cortex-A8 boards in several booths, well outside of mobile phone applications. The ARM Partners are ramping up big-time and I think the world will be completely different this time next year. Last month I observed that Intel’s booth at Mobile World Congress was both uninspiring and comparable in size to Tensilica’s, which felt rather odd. I thought latter’s booth quite nice, by the way (e.g. no offense!). Last year I understand that the Intel presence at Embedded World was somewhat overwhelming with banners touting the next 15 billion intelligent, connected devices by 2015. &amp;nbsp;This year I found Intel’s Embedded World booth smallish and uninspiring. Something is happening here…could they be beginning to pull back? Anyway, the key questions I pondered throughout Embedded World included:  Why is the embedded world so fragmented? Why/where will proprietary architectures (Intel and many others) be successful? Why/where will the ARM architecture (through the Partnership, of course) be successful? Is one model inherently better than the other in this space?]]></description>
			<pubDate>Mon, 08 Mar 2010 09:58:00 GMT</pubDate>
			<category domain="">Industry Expert Blogs</category>
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			<title><![CDATA[Semiconductor IP: lntel vs. ARM and Tessera's Expiring Patent (Entrepreneur Journeys - Sramana Mitra)]]></title>
			<link>http://www.design-reuse.com/go2/722887/1</link>
			<description><![CDATA[The Intel–ARM rivalry is getting interesting. Last year, ARM (NASDAQ:ARMH) unveiled its processor for netbooks and was perceived as a threat to Intel. And this year, Intel responded with an LG smartphone built on its Atom Moorestown platform. Let’s take a closer look at ARM and the other semiconductor IP players, Tessera (NASDAQ:TSRA) and InterDigital (NASDAQ:IDCC).]]></description>
			<pubDate>Mon, 08 Mar 2010 09:40:00 GMT</pubDate>
			<category domain="">Industry Expert Blogs</category>
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			<title><![CDATA[Viewpoint: The importance of FPGA-to-ASIC solutions to accelerate CPU-based protocols ]]></title>
			<link>http://www.design-reuse.com/go2/322876/1</link>
			<description><![CDATA[Joe Rash of CebaTech argues for protocol acceleration solutions, which leverage the capabilities afforded by FPGAs, to help customers get to market fast and capture market opportunities.]]></description>
			<pubDate>Thu, 04 Mar 2010 16:20:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[Embedded Symmetric MultiProcessing system on a SoC with 1.6GHz PowerPC IP in 45nm]]></title>
			<link>http://www.design-reuse.com/go2/322839/1</link>
			<description><![CDATA[Because the dimensions of lithography are now closer to the fundamental physical limits, scaling is more and more difficult and thus multi-core processor solutions are just starting to be more popular in the embedded area. This paper describes in details the features that allow SoCs to be built with up to eight 1.6 GHz PowerPC CPU cores in an embedded system supporting Symmetric Multiprocessing (SMP) architecture. The balancing between CPU execution speed, memory bandwidth and latency, and coherency overhead has been the objective of the design of the PLB6 and the L2 Cache IP's, to reduce as much as possible the drop-off in performance-per-core inherent in an SMP approach.]]></description>
			<pubDate>Mon, 01 Mar 2010 10:34:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[Evolving to a Total IP Solutions to Accelerate SoC Design]]></title>
			<link>http://www.design-reuse.com/go2/322838/1</link>
			<description><![CDATA[With validation and software development becoming a prominent bottleneck in a project, progressive IP providers such as Arasan Chip Systems offer a Total IP Solution to address these demands. In this paper we explore the evolving SoC design model and propose a Total IP Solution approach as the next logical step for IP product companies. ]]></description>
			<pubDate>Mon, 01 Mar 2010 09:51:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[Time to market is a critical consideration]]></title>
			<link>http://www.design-reuse.com/go2/322852/1</link>
			<description><![CDATA[Being first is key, unless you can be substantially better. Being third means being out of luck.]]></description>
			<pubDate>Mon, 01 Mar 2010 04:53:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[Software Architecture for IP verification in Operating System environment]]></title>
			<link>http://www.design-reuse.com/go2/322825/1</link>
			<description><![CDATA[This paper presents versatile software architecture for IP verification in an integrated system environment. The proposed architecture is re-usable across various IP’s and operating platforms. This software architecture speeds up the IP verification process by identifying common ground work required for various IP’s. Further the paper defines standards for the FPGA verification software and develops a prototype on a particular operating platform based on the suggested standards.
]]></description>
			<pubDate>Thu, 25 Feb 2010 15:26:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[Hardware Solutions to the Challenges of Multimedia IP Functional Verification]]></title>
			<link>http://www.design-reuse.com/go2/322786/1</link>
			<description><![CDATA[This paper discusses the functional verification of IP cores and problems which arise during their implemenation in today’s advanced applications. First, the usual approach to functional verification is presented together with its common difficulties. The next part features an example of hardware verification environment which was used for verification of the Evatronix JPEG 2000 encoder multimedia IP core in order to illustrate this paper’s thesis. After a short description of the JPEG 2000 image compression algorithm, the structure of the environment is presented. Then the manner of test cases preparation is described as well as criteria used to determine whether a particular test is passed or failed. Finally, numerical results of hardware verification experiment are presented with some comments which conclude the paper.]]></description>
			<pubDate>Mon, 22 Feb 2010 15:47:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[High-level synthesis, verification and language ]]></title>
			<link>http://www.design-reuse.com/go2/322796/1</link>
			<description><![CDATA[The preferred high-level design methodology proceeds from high-level code to RTL code. Good verification practice requires that the input to High-level Synthesis (HLS) be verified first, via simulation (or some other analytical means), and then the output of HLS be verified, again via simulation or some other means. Using SystemC as the input language to HLS enables this flow, but using C as the HLS input language imposes a serious limitation on doing verification this way.]]></description>
			<pubDate>Mon, 22 Feb 2010 11:10:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[Analog and Mixed Signal Modeling Approaches]]></title>
			<link>http://www.design-reuse.com/go2/322773/1</link>
			<description><![CDATA[This article provides an insight into various approaches followed for Analog and Mixed Signal (AMS) modeling and the associated challenges. The emphasis is on analyzing various approaches and finally providing options that can be used right from architectural exploration to implementation with a co-simulation based approach.]]></description>
			<pubDate>Mon, 22 Feb 2010 10:06:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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