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		<title>Design And Reuse</title>
		<link>http://www.design-reuse.com/</link>
		<description>The industry source for engineers and technical managers worldwide.</description>
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		<copyright>Copyright 2005, Design And Reuse S.A.</copyright>
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		<title>Design And Reuse</title> 
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		<!-- CONTENT -->
	
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			<title><![CDATA[Achronix Completes First Close of $52 Million Series B Preferred Stock Financing]]></title>
			<link>http://www.design-reuse.com/go2/419320/1</link>
			<description><![CDATA[The proceeds from the financing will be used to fund the development of next-generation products and to support the rapidly accelerating demand for the recently-announced Speedster family of 1.5 GHz FPGAs.]]></description>
			<pubDate>Wed, 15 Oct 2008 14:57:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Cadence Expands Enterprise Verification IP Portfolio by 5X to Provide Industry's Broadest OVM Multi-Language Offering]]></title>
			<link>http://www.design-reuse.com/go2/419317/1</link>
			<description><![CDATA[VIP Portfolio Extends to Over 30 Industry-Standard Protocols, Enabling Customers to Improve Schedule Predictability, Productivity, and Product Quality]]></description>
			<pubDate>Wed, 15 Oct 2008 14:29:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Cadence Board of Directors Creates Interim Office of the Chief Executive; Michael Fister Resigns]]></title>
			<link>http://www.design-reuse.com/go2/419316/1</link>
			<description><![CDATA[The formation of the Interim Office of the Chief Executive followed Michael Fister’s resignation as President, Chief Executive Officer and a director of the company, by mutual agreement between Mr. Fister and the Board.]]></description>
			<pubDate>Wed, 15 Oct 2008 14:24:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[LogicVision Reports Management Changes]]></title>
			<link>http://www.design-reuse.com/go2/419315/1</link>
			<description><![CDATA[The three departing executives are Bruce M. Jaffe, Vice President, Finance and CFO, Farhad Hayat, Vice President, Marketing, and Ronald H. Mabry, Vice President, Field Operations and Application Engineering.
]]></description>
			<pubDate>Wed, 15 Oct 2008 10:50:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Altera Announces Third Quarter Results]]></title>
			<link>http://www.design-reuse.com/go2/419314/1</link>
			<description><![CDATA[Altera today announced third quarter sales of $356.8 million, down 1 percent from the second quarter of 2008 and up 13 percent from the third quarter of 2007]]></description>
			<pubDate>Wed, 15 Oct 2008 10:42:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Maxim Integrated Products Announces Acquisition of Digital Video Leader Mobilygen]]></title>
			<link>http://www.design-reuse.com/go2/419313/1</link>
			<description><![CDATA[Maxim today announced that it has entered into a definitive agreement to purchase Mobilygen, a privately held, fabless semiconductor company with leading technology in H.264 video compression]]></description>
			<pubDate>Wed, 15 Oct 2008 10:27:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[UBIDYNE Selects JAZZ Semiconductor's 0.18-micron SiGe BICMOS process to develop world's first pure digital radio system]]></title>
			<link>http://www.design-reuse.com/go2/419318/1</link>
			<description><![CDATA[Ubidyne’s Micro-Radio Enables Mobile Infrastructure Equipment Vendors Worldwide to Significantly Improve Performance, Flexibility and Coverage]]></description>
			<pubDate>Wed, 15 Oct 2008 03:47:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[German Court Finds DVD Disc Manufacturer Odeon Infringes MPEG-2 Patents]]></title>
			<link>http://www.design-reuse.com/go2/419319/1</link>
			<description><![CDATA[The District Court Düsseldorf, Germany recently pronounced 12 verdicts finding that DVD disc manufacturer Odeon Cineplex S.A. (“Odeon”) of Greece, has infringed certain MPEG-2 patents as a result of Odeon’s manufacture of DVD video discs.]]></description>
			<pubDate>Wed, 15 Oct 2008 01:51:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Express Logic and Renesas Technology Team to Offer Audio-Video Media Player Reference Design]]></title>
			<link>http://www.design-reuse.com/go2/419311/1</link>
			<description><![CDATA[The media player platform is based on Renesas’ SuperH SH-2A microcontroller architecture and Express Logic’s ThreadX® RTOS, and enables access and display of media from USB flash drives or SD memory cards.]]></description>
			<pubDate>Tue, 14 Oct 2008 17:07:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[MoSys, Inc. Provides Business Update and Announces Stock Repurchase Plan]]></title>
			<link>http://www.design-reuse.com/go2/419310/1</link>
			<description><![CDATA[MoSys today announced preliminary operating results for the third quarter and nine months ended September 30, 2008 with estimated total net revenue ranging from $3.9 million to $4.2 million and an estimated net loss on a GAAP basis ranging from $3.0 million to $3.3 million for the three months ended September 30, 2008.]]></description>
			<pubDate>Tue, 14 Oct 2008 15:35:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Former Samsung Multimedia Lab Chief Joins Denali's Executive Team]]></title>
			<link>http://www.design-reuse.com/go2/419308/1</link>
			<description><![CDATA[Dr. Stephen Oh to Serve as Vice President of Platform Business Development]]></description>
			<pubDate>Tue, 14 Oct 2008 14:33:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Tensilica's Xtensa Customizable Processor Used in Panasonic Mobile’s Wireless Baseband Processor]]></title>
			<link>http://www.design-reuse.com/go2/419307/1</link>
			<description><![CDATA[Tensilica today announced that Panasonic Mobile Communications has licensed the Xtensa LX2 customizable processor core for a baseband processor integrated circuit for mobile phones.]]></description>
			<pubDate>Tue, 14 Oct 2008 14:26:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Evatronix Application-debugging Support Environment for 8051 and 68000 compliant IP cores improved with trace and TCP/IP support]]></title>
			<link>http://www.design-reuse.com/go2/419306/1</link>
			<description><![CDATA[The newest release of the EASE enhances its predecessor functionality by two new features: the configurable real-time trace and the TCP/IP support, hence providing customers with better, faster and more convenient interface between the hardware prototype and the embedded software development environment.]]></description>
			<pubDate>Tue, 14 Oct 2008 13:43:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[HDIC Cooperates with SMIC for Successful Debut of High Definition TV Transmission Chips during Beijing Olympic Games]]></title>
			<link>http://www.design-reuse.com/go2/419309/1</link>
			<description><![CDATA[SMIC  and HDIC recently cooperated on SMIC's 0.13um process to manufacture demodulator chips based on China's terrestrial digital TV standard.]]></description>
			<pubDate>Tue, 14 Oct 2008 06:36:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[IMEC starts new research activities on resistive RAM]]></title>
			<link>http://www.design-reuse.com/go2/419312/1</link>
			<description><![CDATA[Resistive switching memories are based on materials whose resistivity can be electrically switched between high and low conductive states. RRAM is becoming of interest for future scaled memories because of their superior intrinsic scaling characteristics compared to the charge-based Flash devices, and potentially small cell size.]]></description>
			<pubDate>Tue, 14 Oct 2008 04:12:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Toshiba licenses IMEC’s power-efficient, flexible processor technology]]></title>
			<link>http://www.design-reuse.com/go2/419305/1</link>
			<description><![CDATA[IMEC today announced that Toshiba has licensed IMEC technology for designing power-efficient, flexible processors in a single- and multiprocessor architecture. The agreement concerns IMEC’s ADRES reconfigurable processor template, the DRESC compiler, and the MPSoC (multi-processor system-on-chip) suite of design tools. Toshiba will also cooperate with IMEC to develop processors and tools that enable gigabit/s demodulation.]]></description>
			<pubDate>Mon, 13 Oct 2008 21:49:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Xilinx Senior Executive, Patrick Little, Joins Fast Growing eASIC As New CEO]]></title>
			<link>http://www.design-reuse.com/go2/419304/1</link>
			<description><![CDATA[Little joins eASIC from Xilinx, where he served as Senior Vice President of Products and Market Development. Little succeeds Ronnie Vasishta, who remains as President and will assume the additional responsibility of Chief Operation Officer (COO).]]></description>
			<pubDate>Mon, 13 Oct 2008 20:49:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Silicon for better DTV tuning, PIP, speed and size]]></title>
			<link>http://www.design-reuse.com/go2/319301/1</link>
			<description><![CDATA[Silicon tuners now have the edge, and offer feature advantages like inexpensive PIP via time slicing.]]></description>
			<pubDate>Mon, 13 Oct 2008 16:53:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[Innovative Integration Inc, and R-Interface announce a partnership to co-market &amp; develop IP products &amp; hardware for wireless applications]]></title>
			<link>http://www.design-reuse.com/go2/419298/1</link>
			<description><![CDATA[The agreement allows Innovative and R-Interface to offer complete solutions for software-defined radio (SDR) applications by integrating R-Interfaces IP for software defined radio (SDR) with Innovatives high performance X5 family of digitizers and powerful application development tools for SDR development.]]></description>
			<pubDate>Mon, 13 Oct 2008 15:00:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[INSIDE Contactless and TIEMPO Announce Partnership on Next Generation Chip Product]]></title>
			<link>http://www.design-reuse.com/go2/419297/1</link>
			<description><![CDATA[INSIDE Contactless, the world leader in advanced contactless microprocessor platforms, and TIEMPO, an innovative IP company specialized in the design of asynchronous ICs, have announced a partnership for the design of a next generation chip product that incorporates asynchronous design technology.]]></description>
			<pubDate>Mon, 13 Oct 2008 14:56:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[Alma Technologies to integrate Scalado SpeedTags technology in its JPEG products]]></title>
			<link>http://www.design-reuse.com/go2/419296/1</link>
			<description><![CDATA[Scalado and Alma Technologies  have today announced details of the first JPEG compression IP core supporting Scalado SpeedTags™ technology.]]></description>
			<pubDate>Mon, 13 Oct 2008 14:39:00 GMT</pubDate>
			<category domain="">Headline News</category>
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			<title><![CDATA[What's your sine? Finding the right algorithm for digital frequency synthesis on a DSP]]></title>
			<link>http://www.design-reuse.com/go2/319295/1</link>
			<description><![CDATA[A new approach to direct digital frequency synthesis uses a combination of lookup tables and trigonometric identities that lends itself to more efficient implementation on digital signal processors.]]></description>
			<pubDate>Mon, 13 Oct 2008 14:31:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[Full HD 1080p Video Codec Integrated Solution from videantis]]></title>
			<link>http://www.design-reuse.com/go2/119294/1</link>
			<description><![CDATA[Full HD 1080p Video Codec Integrated Solution from videantis]]></description>
			<pubDate>Mon, 13 Oct 2008 14:26:00 GMT</pubDate>
			<category domain="">New Products</category>
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			<title><![CDATA[12-bit 100 Msps ADC 20mW in 65nm from IQ-Analog]]></title>
			<link>http://www.design-reuse.com/go2/119286/1</link>
			<description><![CDATA[12-bit 100 Msps ADC 20mW in 65nm from IQ-Analog]]></description>
			<pubDate>Mon, 13 Oct 2008 10:55:00 GMT</pubDate>
			<category domain="">New Products</category>
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			<title><![CDATA[DVB Common Scrambling Algorithm (CSA) core from Helion Technology]]></title>
			<link>http://www.design-reuse.com/go2/119293/1</link>
			<description><![CDATA[DVB Common Scrambling Algorithm (CSA) core from Helion Technology]]></description>
			<pubDate>Mon, 13 Oct 2008 08:24:00 GMT</pubDate>
			<category domain="">New Products</category>
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			<title><![CDATA[Replacing obsolete video game circuits with Xilinx CPLDs]]></title>
			<link>http://www.design-reuse.com/go2/319280/1</link>
			<description><![CDATA[In this article, the author replaces a defective part in a 1980s game system to show his employer that they can replace a range of parts that vendors are no longer producing.]]></description>
			<pubDate>Thu, 09 Oct 2008 17:29:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[Low Power Transport Demultiplexer for ATSC and DVB Broadcast Format]]></title>
			<link>http://www.design-reuse.com/go2/319279/1</link>
			<description><![CDATA[In this paper, we developed low power transport demultiplexer to support MPEG-2 transport streams for ATSC and DVB digital broadcast standards. Novel window based packet identification (PID) and section filtering is presented to provide a cost effective and flexible solution.]]></description>
			<pubDate>Thu, 09 Oct 2008 17:11:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[WiMAX PHY solution from Coresonic]]></title>
			<link>http://www.design-reuse.com/go2/119276/1</link>
			<description><![CDATA[WiMAX PHY solution from Coresonic]]></description>
			<pubDate>Thu, 09 Oct 2008 16:21:00 GMT</pubDate>
			<category domain="">New Products</category>
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			<title><![CDATA[Adaptative MPEG TS bitrate from Multi Video Designs]]></title>
			<link>http://www.design-reuse.com/go2/119277/1</link>
			<description><![CDATA[Adaptative MPEG TS bitrate from Multi Video Designs]]></description>
			<pubDate>Thu, 09 Oct 2008 14:25:00 GMT</pubDate>
			<category domain="">New Products</category>
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			<title><![CDATA[Ultra high-Speed Acquisition Board (3Gsample) from BitSim]]></title>
			<link>http://www.design-reuse.com/go2/119278/1</link>
			<description><![CDATA[Ultra high-Speed Acquisition Board (3Gsample) from BitSim]]></description>
			<pubDate>Thu, 09 Oct 2008 11:30:00 GMT</pubDate>
			<category domain="">New Products</category>
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			<title><![CDATA[EDA needs functional qualification]]></title>
			<link>http://www.design-reuse.com/go2/319261/1</link>
			<description><![CDATA[EDA needs functional qualification, a new category of EDA product. The technology is fundamentally different from existing coverage technologies. The implications for the verification profession could be radical.  ]]></description>
			<pubDate>Wed, 08 Oct 2008 14:14:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[JPEG 2000 Encoder &amp; Decoder Development Kit from intoPIX]]></title>
			<link>http://www.design-reuse.com/go2/119248/1</link>
			<description><![CDATA[JPEG 2000 Encoder &amp; Decoder Development Kit from intoPIX]]></description>
			<pubDate>Tue, 07 Oct 2008 06:26:00 GMT</pubDate>
			<category domain="">New Products</category>
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			<title><![CDATA[The need to address power during manufacturing test]]></title>
			<link>http://www.design-reuse.com/go2/319246/1</link>
			<description><![CDATA[Until recently, the idea of managing power during manufacturing test has been a secondary concern. But with shrinking geometries and lower voltage thresholds comes an increasing awareness that excessive power consumption during test can have an impact on digital IC reliability.]]></description>
			<pubDate>Mon, 06 Oct 2008 17:43:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[Audio ADC buffer design secrets: Interfacing to audio ADC sampling circuits]]></title>
			<link>http://www.design-reuse.com/go2/319234/1</link>
			<description><![CDATA[Effectively interfacing to A/D converter sampling networks can be a challenging undertaking, but undertsanding the fundamentals can help ensure a successful design.]]></description>
			<pubDate>Mon, 06 Oct 2008 10:11:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[Real-time JPEG 2000 Decoder Core for high-speed applications (up to multi-channel DCI 2K and 4K, HD 1080i and 1080p) from Barco Silex]]></title>
			<link>http://www.design-reuse.com/go2/119233/1</link>
			<description><![CDATA[Real-time JPEG 2000 Decoder Core for high-speed applications (up to multi-channel DCI 2K and 4K, HD 1080i and 1080p) from Barco Silex]]></description>
			<pubDate>Mon, 06 Oct 2008 09:32:00 GMT</pubDate>
			<category domain="">New Products</category>
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			<title><![CDATA[12-bit, 80 MHz, 2.5 V Current Steering IQDAC, for Tx path in LTE systems, also suitable for WiMAX in TSMC 65nm LP from MIPS Technologies]]></title>
			<link>http://www.design-reuse.com/go2/119230/1</link>
			<description><![CDATA[12-bit, 80 MHz, 2.5 V Current Steering IQDAC, for Tx path in LTE systems, also suitable for WiMAX in TSMC 65nm LP from MIPS Technologies]]></description>
			<pubDate>Mon, 06 Oct 2008 08:20:00 GMT</pubDate>
			<category domain="">New Products</category>
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			<title><![CDATA[Step Down DC/DC Converter in TSMC 65nm LP from Silicon &amp; Software Systems]]></title>
			<link>http://www.design-reuse.com/go2/119229/1</link>
			<description><![CDATA[Step Down DC/DC Converter in TSMC 65nm LP from Silicon &amp; Software Systems]]></description>
			<pubDate>Mon, 06 Oct 2008 07:50:00 GMT</pubDate>
			<category domain="">New Products</category>
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			<title><![CDATA[In multicore SOC architectures, buses are a last resort]]></title>
			<link>http://www.design-reuse.com/go2/319221/1</link>
			<description><![CDATA[The one-processor system model that dominated electronic system design since 1971 is now thoroughly obsolete. Today's SOC designers readily accept the idea of using multiple processors in their complex systems to achieve design goals and use the terms &quot;control plane&quot; and &quot;data plane&quot; to describe how these various on-chip processors are used on the chip.]]></description>
			<pubDate>Thu, 02 Oct 2008 17:22:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[How to transform silicon with dynamic reconfiguration]]></title>
			<link>http://www.design-reuse.com/go2/319199/1</link>
			<description><![CDATA[A microcontroller capable of reconfiguring its resources needs to provide the integration of an ASIC with the configurability of a FPGA...]]></description>
			<pubDate>Thu, 02 Oct 2008 08:01:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[Measuring Quality in Semiconductor IP]]></title>
			<link>http://www.design-reuse.com/go2/319187/1</link>
			<description><![CDATA[Semiconductor IP reuse can yield a 2x improvement in design productivity for semiconductor companies. However, with these startling productivity gains come integration pain. Why?]]></description>
			<pubDate>Mon, 29 Sep 2008 17:26:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[IP Gate Count Estimation Methodology during Micro-Architecture Phase]]></title>
			<link>http://www.design-reuse.com/go2/319171/1</link>
			<description><![CDATA[This paper presents challenges of gate count estimation during early architecture design phase along with effective methodology. This paper is backed up with vast experience of various IP designs with logic area up-to several hundreds of kilo gates with several hundred kilo bits of memory.]]></description>
			<pubDate>Mon, 29 Sep 2008 12:01:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[Using micro-benchmarks to evaluate &amp; compare Networks-on-chip MPSoC designs]]></title>
			<link>http://www.design-reuse.com/go2/319172/1</link>
			<description><![CDATA[Network-on-Chip (NoC) has been recognized as a promising architecture to accommodate tens, hundreds or even thousand of cores. As a result, a number of NoC architectures have been and are being proposed.]]></description>
			<pubDate>Mon, 29 Sep 2008 11:23:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[How to use FPGAs to develop an intelligent solar tracking system]]></title>
			<link>http://www.design-reuse.com/go2/319155/1</link>
			<description><![CDATA[This article examines the design advantages of creating an intelligent solar tracking system using an embedded processor and an FPGA in a system-on-a-chip (SOC) architecture.]]></description>
			<pubDate>Thu, 25 Sep 2008 16:08:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[Choosing the right low power processor for your embedded design]]></title>
			<link>http://www.design-reuse.com/go2/319142/1</link>
			<description><![CDATA[Key selection criteria show where various low power processors best fit]]></description>
			<pubDate>Wed, 24 Sep 2008 17:33:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[Enabling Robust and Flexible SOC Designs with AXI to PCIe Bridge Solutions]]></title>
			<link>http://www.design-reuse.com/go2/319132/1</link>
			<description><![CDATA[A bridge between two standard protocols is an attractive building block for system designers. When designing an application around a standard protocol, a bridge to another protocol enables all of the benefits of that second system with a less-intensive design-process.]]></description>
			<pubDate>Tue, 23 Sep 2008 14:49:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[Implementing the right audio/video transcoding scheme in consumer SoC devices]]></title>
			<link>http://www.design-reuse.com/go2/319129/1</link>
			<description><![CDATA[In this &quot;how we did it,&quot; Tim Simerly describes the factors TI engineers took into account to accommodate the many encoding formats in a home entertainment network when designing the DaVinci family of SoC processors.]]></description>
			<pubDate>Tue, 23 Sep 2008 13:53:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[ Bridging the DFT and Product Engineering Gap to Achieve Early Silicon Validation]]></title>
			<link>http://www.design-reuse.com/go2/319120/1</link>
			<description><![CDATA[This paper introduces a unified DFT - PE Methodology, aimed at providing a complete, methodical and fully automated path addressing gaps between DFT and PE team ensuring quick turnaround time in silicon validation. ]]></description>
			<pubDate>Mon, 22 Sep 2008 16:13:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[Using static analysis to diagnose &amp; prevent failures in safety-critical device designs]]></title>
			<link>http://www.design-reuse.com/go2/319108/1</link>
			<description><![CDATA[David Kleidermacher reviews static analysis tools and their usefulness in safety-critical embedded apps such as medical devices and systems, and provides insight into using them effectively and assesses what remains to be done to address future challenges.]]></description>
			<pubDate>Thu, 18 Sep 2008 17:22:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[How to defend against the cloning of your FPGA designs]]></title>
			<link>http://www.design-reuse.com/go2/319101/1</link>
			<description><![CDATA[This article describes a new way of tagging designs to help to counter the rapidly growing trade in stolen IP and cloned designs. The topic is a difficult one for the industry to discuss; recently, however, more and more voices have been raised on the issue.]]></description>
			<pubDate>Thu, 18 Sep 2008 15:30:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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			<title><![CDATA[Systolic FIR Filter Based FPGA ]]></title>
			<link>http://www.design-reuse.com/go2/319106/1</link>
			<description><![CDATA[In this paper, we review in detail the basic building blocks of reconfigurable devices, essentially, the field-programmable gate arrays, then we describes a high-speed, reconfigurable Systolic Finite Impulse Response Filter design implemented in the Virtex-II series of FPGAs. ]]></description>
			<pubDate>Thu, 18 Sep 2008 12:05:00 GMT</pubDate>
			<category domain="">Industry Articles</category>
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