<?xml version="1.0" encoding="iso-8859-1"?>
		<rss version="2.0" xmlns:content="http://purl.org/rss/1.0/modules/content/">
		<channel>
		<title>Design And Reuse - Industry Articles</title>
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		<description>The industry source for engineers and technical managers worldwide.</description>
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			<title><![CDATA[Generic DDR Behavioural Model]]></title>
			<link>http://www.design-reuse.com/articles/32072/generic-ddr-behavioural-model.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=32072</link>
			<description><![CDATA[This paper represents a generic executable architecture. It represents the efficient behaviour of the Memory Model to be used for verification of SOC communicating with DDR SDRAMs or can be used as the third party Model verification (passive element). Paper shows the capability as standalone VIP architecture and also represents the market value of DDR model in the present technical era with different technical views and challenges faced. It also givessolution of supporting different part number of established DDR vendors like Micron, Elpida, Samsung etc.<br>View the full article <a href="http://www.design-reuse.com/articles/32072/generic-ddr-behavioural-model.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=32072">HERE</a>]]></description>
			<pubDate>Mon, 20 May 2013 14:13:00 GMT</pubDate>
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			<title><![CDATA[Design planning for large SoC implementation at 40nm: Guaranteeing predictable schedule and first-pass silicon success]]></title>
			<link>http://www.design-reuse.com/articles/32066/design-planning-for-large-soc-implementation-at-40nm.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=32066</link>
			<description><![CDATA[Modern SoC development requires a holistic approach and thorough planning starting at the design architecture of the SoC. The ASIC implementation process has to keep pace with the design complexity, performance, and time-to-market, all while ensuring first-time silicon success. <br>View the full article <a href="http://www.design-reuse.com/articles/32066/design-planning-for-large-soc-implementation-at-40nm.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=32066">HERE</a>]]></description>
			<pubDate>Mon, 20 May 2013 09:06:00 GMT</pubDate>
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			<title><![CDATA[All eyes on Zynq SoC for smarter vision]]></title>
			<link>http://www.design-reuse.com/articles/32062/all-eyes-on-zynq-soc-for-smarter-vision.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=32062</link>
			<description><![CDATA[The Zynq All Programmable SoC, in tandem with new Xilinx tools and IP, forms the foundation for the next generation of embedded vision products.<br>View the full article <a href="http://www.design-reuse.com/articles/32062/all-eyes-on-zynq-soc-for-smarter-vision.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=32062">HERE</a>]]></description>
			<pubDate>Fri, 17 May 2013 09:12:00 GMT</pubDate>
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			<title><![CDATA[Moving to SystemC TLM for design and verification of digital hardware]]></title>
			<link>http://www.design-reuse.com/articles/32029/moving-to-systemc-tlm-for-design-and-verification-of-digital-hardware.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=32029</link>
			<description><![CDATA[By moving to SystemC TLM as the design entry point, and by leveraging high-level synthesis in combination with IP reuse, designers can handle growing design and verification complexity, time-to-market pressures, power goals, and evolving design specifications…<br>View the full article <a href="http://www.design-reuse.com/articles/32029/moving-to-systemc-tlm-for-design-and-verification-of-digital-hardware.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=32029">HERE</a>]]></description>
			<pubDate>Mon, 13 May 2013 16:24:00 GMT</pubDate>
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			<title><![CDATA[Automated ECO Flow for overall cycle time reduction]]></title>
			<link>http://www.design-reuse.com/articles/32027/automated-eco-flow-for-overall-cycle-time-reduction.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=32027</link>
			<description><![CDATA[Engineering Change Order or ECO is the process of inserting logic directly into the gate level netlist corresponding to a change that occurs in the rtl due to design error fixes or a change request from the customer. ECO is preferred as they save time and money in comparison to a full chip re-spin. Some of these ECOs come very late in the design cycle, some of them have high level of complexity involved and at such times the need for an automated tool becomes a necessity. The idea proposed in the paper addresses this very issue. With this idea even complex ECOs can be implemented automatically in lesser turnaround time.<br>View the full article <a href="http://www.design-reuse.com/articles/32027/automated-eco-flow-for-overall-cycle-time-reduction.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=32027">HERE</a>]]></description>
			<pubDate>Mon, 13 May 2013 15:25:00 GMT</pubDate>
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			<title><![CDATA[The TV Studio Becomes a System]]></title>
			<link>http://www.design-reuse.com/articles/32025/the-tv-studio-becomes-a-system.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=32025</link>
			<description><![CDATA[Change is sweeping across the video production studio. High-definition (HD), ultra-high-definition (UHD), video over coaxial cable (or “coax”), video over Ethernet, digital post-production: the gusts of change are relentless. And while the basic functions of the studio remain unchanged since the days when Walter Cronkite first turned his reassuring yet saturnine gaze toward a camera, the way these functions are implemented and the architectures in which they reside are all in directed turmoil.<br>View the full article <a href="http://www.design-reuse.com/articles/32025/the-tv-studio-becomes-a-system.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=32025">HERE</a>]]></description>
			<pubDate>Mon, 13 May 2013 14:54:00 GMT</pubDate>
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			<title><![CDATA[A consumer reports methodology for IP]]></title>
			<link>http://www.design-reuse.com/articles/32011/a-consumer-reports-methodology-for-ip.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=32011</link>
			<description><![CDATA[As an SoC designer, you’re probably frustrated by how IP (3rd party and internal) can hinder your design getting to tapeout. After all, IP is supposed to be the cure-all for increasingly-complex SoC designs, right?   However, it’s turned into a sometimes endless, difficult series of IP fixes.  Why?<br>View the full article <a href="http://www.design-reuse.com/articles/32011/a-consumer-reports-methodology-for-ip.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=32011">HERE</a>]]></description>
			<pubDate>Thu, 09 May 2013 16:06:00 GMT</pubDate>
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			<title><![CDATA[Synthesis-aware clock analysis and constraints generation]]></title>
			<link>http://www.design-reuse.com/articles/32004/synthesis-aware-clock-analysis-constraints-generation.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=32004</link>
			<description><![CDATA[The intentions of a clock tree synthesis (CTS) tool are to create a balanced clock network with short insertion delay, smaller skews, and as few buffers as possible...<br>View the full article <a href="http://www.design-reuse.com/articles/32004/synthesis-aware-clock-analysis-constraints-generation.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=32004">HERE</a>]]></description>
			<pubDate>Tue, 07 May 2013 16:03:00 GMT</pubDate>
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			<title><![CDATA[SoC Interconnect Verification Challenge]]></title>
			<link>http://www.design-reuse.com/articles/31993/soc-interconnect-verification-challenge.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=31993</link>
			<description><![CDATA[This paper describes the author’s experiences in verifying multi-protocol SoC interconnects, it explains the pitfalls of such verification and describes a solution to allow easy reconfiguration of a generic verification environment. We show how issues have been resolved and propose a generic approach for SoC interconnect verification.<br>View the full article <a href="http://www.design-reuse.com/articles/31993/soc-interconnect-verification-challenge.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=31993">HERE</a>]]></description>
			<pubDate>Mon, 06 May 2013 15:32:00 GMT</pubDate>
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			<title><![CDATA[How small vendors compete in analog IC market]]></title>
			<link>http://www.design-reuse.com/articles/31975/how-small-vendors-compete-in-analog-ic-market.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=31975</link>
			<description><![CDATA[Can a small fabless analog vendor compete with the top five analog IC vendors in global markets? This question is being asked often, especially in the context of emerging Chinese end-system OEMs. Europe used to have many small analog IC specialists – most but not all have by now been acquired. In this case study, we will compare one such small but well-established company competing with the world’s largest analog company.<br>View the full article <a href="http://www.design-reuse.com/articles/31975/how-small-vendors-compete-in-analog-ic-market.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=31975">HERE</a>]]></description>
			<pubDate>Thu, 02 May 2013 09:56:00 GMT</pubDate>
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			<title><![CDATA[Improving ASIP code generation and back-end compilation: Part 2]]></title>
			<link>http://www.design-reuse.com/articles/31955/improving-asip-code-generation-and-back-end-compilation.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=31955</link>
			<description><![CDATA[In a two part article from High Performance Embedded Computing, author Wayne Wolf provides a review of some of the most effective ways to improve the code performance and reliability. Part 2: instruction selection and modeling and code placement.<br>View the full article <a href="http://www.design-reuse.com/articles/31955/improving-asip-code-generation-and-back-end-compilation.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=31955">HERE</a>]]></description>
			<pubDate>Mon, 29 Apr 2013 16:11:00 GMT</pubDate>
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			<title><![CDATA[Intellectual property security: A challenge for embedded systems developers]]></title>
			<link>http://www.design-reuse.com/articles/31954/intellectual-property-security-embedded-systems.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=31954</link>
			<description><![CDATA[A company’s success - and its future - depends on the creation and successful defense of intellectual property (IP), which is generally defined as &quot;creations of the mind for which exclusive rights are recognized.” IP is the outcome of innovation and work done by an organization/person and gives a company's products an edge over competitors. <br>View the full article <a href="http://www.design-reuse.com/articles/31954/intellectual-property-security-embedded-systems.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=31954">HERE</a>]]></description>
			<pubDate>Mon, 29 Apr 2013 16:09:00 GMT</pubDate>
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			<title><![CDATA[The Power of Developing Hardware and Software in Parallel ]]></title>
			<link>http://www.design-reuse.com/articles/31951/the-power-of-developing-hardware-and-software-in-parallel.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=31951</link>
			<description><![CDATA[As the mobile development cycles keep shrinking, innovative companies are using a number of strategies to balance complexity of software development with aggressive schedules.  Starting software development early and getting to market early is one of the strategies that innovative mobile software developers are using to beat the clock.  By following a phased development process, sharing early work with customers and their ecosystem partners, mobile devices are reaching market earlier and with innovative features.   <br>View the full article <a href="http://www.design-reuse.com/articles/31951/the-power-of-developing-hardware-and-software-in-parallel.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=31951">HERE</a>]]></description>
			<pubDate>Mon, 29 Apr 2013 14:49:00 GMT</pubDate>
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			<title><![CDATA[Using audio codecs IP as the digital audio hub in mobile multimedia systems]]></title>
			<link>http://www.design-reuse.com/articles/31927/using-audio-codecs-ip.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=31927</link>
			<description><![CDATA[By integrating an audio analog codec that implements the 'audio hub' functionality and is able to process and mix audio signals from asynchronous sources, system designers can free the scarce main processor resources for more relevant tasks and simplify the system design, thus achieving a more effective solution.<br>View the full article <a href="http://www.design-reuse.com/articles/31927/using-audio-codecs-ip.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=31927">HERE</a>]]></description>
			<pubDate>Wed, 24 Apr 2013 09:15:00 GMT</pubDate>
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			<title><![CDATA[A Low Complexity Parallel Architecture of Turbo Decoder Based on QPP Interleaver for 3GPP-LTE/LTE-A]]></title>
			<link>http://www.design-reuse.com/articles/31907/turbo-decoder-architecture-qpp-interleaver-3gpp-lte-lte-a.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=31907</link>
			<description><![CDATA[This paper propose an improved method called the modified warm-up-free parallel window(PW) MAP decoding schemes to implement highly-parallel Turbo decoder architecture based on the QPP(Quadratic Polynomial Permutation) interleaver of 3GPP LTE/LTE-A standards. <br>View the full article <a href="http://www.design-reuse.com/articles/31907/turbo-decoder-architecture-qpp-interleaver-3gpp-lte-lte-a.html?utm_medium=rss&amp;utm_source=designreuse&amp;utm_content=1&amp;utm_campaign=31907">HERE</a>]]></description>
			<pubDate>Mon, 22 Apr 2013 14:14:00 GMT</pubDate>
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		</channel>
		</rss>
	