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		<title>Design And Reuse - Industry Articles</title>
		<link>http://www.design-reuse.com/</link>
		<description>The industry source for engineers and technical managers worldwide.</description>
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		<copyright>Copyright 2007, Design And Reuse S.A.</copyright>
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		<title>Design And Reuse - Industry Articles</title> 
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			<title><![CDATA[PRODUCT HOW-TO: The care and feeding of embedded Linux running on MIPS CPUs]]></title>
			<link>http://www.design-reuse.com/go2/321020/1</link>
			<description><![CDATA[An update on the use of Linux in many embedded consumer and networking applications and how MIPS Technologies hardware and software can be used to make the development process easier.]]></description>
			<pubDate>Thu, 02 Jul 2009 10:01:00 GMT</pubDate>
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			<title><![CDATA[Clock Mesh Variation Robustness: Benefits and Analysis]]></title>
			<link>http://www.design-reuse.com/go2/321019/1</link>
			<description><![CDATA[Circuit delay is increasingly affected by process variations at lower technology nodes. Technologies that offer variation tolerance boost design performance and productivity.  This article gives an overview and highlights the benefits of clock mesh technology compared to conventional clock tree methods.]]></description>
			<pubDate>Thu, 02 Jul 2009 09:37:00 GMT</pubDate>
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			<title><![CDATA[Rapid debug of serial buses in FPGAs ]]></title>
			<link>http://www.design-reuse.com/go2/321010/1</link>
			<description><![CDATA[Low-speed serial buses remain prevalent across several electronics industries. Serial buses such as I2C, SPI, CAN, LIN, and RS-232 are often key points for debugging designs with FPGAs which higher speed serial buses quickly pass data from chip to chip. Historically, capturing and decoding the information required significant manual effort if using an oscilloscope or the purchase of custom tools. Oscilloscope vendors now incorporate significant application technology that simplifies debug of low-speed serial buses.]]></description>
			<pubDate>Wed, 01 Jul 2009 11:14:00 GMT</pubDate>
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			<title><![CDATA[Embedded Software Architecture Specification Developments in Support of SoC Design and Re-use]]></title>
			<link>http://www.design-reuse.com/go2/320994/1</link>
			<description><![CDATA[This paper reviews the open literature on general software architecture highlighting techniques applicable to the embedded domain. These areas include use of multiple views, hierarchical patterns, standard modeling, advanced documentation and application of architecture assistance tools. Applying software architecture for embedded re-use is an area identified as not being fully explored in current literature. ]]></description>
			<pubDate>Mon, 29 Jun 2009 16:06:00 GMT</pubDate>
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			<title><![CDATA[Debugging of embedded Linux applications on ARM9/ARM11 processors ]]></title>
			<link>http://www.design-reuse.com/go2/320982/1</link>
			<description><![CDATA[Embedded Linux as an operating system for modern ARM processors? Maybe not such a bad idea? Linux is a multitasking operating system and therefore, each process must be assigned its own process address space. However, this partitioning greatly complicates the debugging of processors and inter-process functionality. So what can be done to tackle this? This article illustrates some possibilities how you can successfully achieve your goal.]]></description>
			<pubDate>Thu, 25 Jun 2009 16:28:00 GMT</pubDate>
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			<title><![CDATA[Modelling Embedded Systems at Functional Untimed Application Level]]></title>
			<link>http://www.design-reuse.com/go2/318418/1</link>
			<description><![CDATA[We propose a structured methodology to allow flexible, accurate and fast system modelling at Functional Untimed Application Level. The methodology is built on 4 levels of abstraction, from the IP Level up to the Use-case Level, where the bottom level gives us accuracy, while the top gives us speed.]]></description>
			<pubDate>Thu, 25 Jun 2009 16:01:00 GMT</pubDate>
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			<title><![CDATA[Viewpoint: Capture OCP systems in IP-XACT 1.4 ]]></title>
			<link>http://www.design-reuse.com/go2/320957/1</link>
			<description><![CDATA[A complete standardization process describing how OCP cores and systems can be captured in IP-XACT is a desired end goal.]]></description>
			<pubDate>Tue, 23 Jun 2009 07:36:00 GMT</pubDate>
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			<title><![CDATA[Managing an Adaptive Verification Environment with the Open Verification Methodology]]></title>
			<link>http://www.design-reuse.com/go2/320950/1</link>
			<description><![CDATA[The OVM provides a built-in mechanism to statically configure verification components. The verification parameters can be used to control the verification environment topology as well as trigger specific behaviors. In some cases the configuration of the verification environment cannot be predefined at build time. In such cases, the verification components need to adapt their configuration, and hence their behavior, dynamically. For example, the verification environment configuration might be based on the register configuration of the design under verification (DUV) ]]></description>
			<pubDate>Mon, 22 Jun 2009 11:25:00 GMT</pubDate>
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			<title><![CDATA[SuperSpeed USB 3.0: Ubiquitous Interconnect for Next Generation Consumer Applications]]></title>
			<link>http://www.design-reuse.com/go2/320937/1</link>
			<description><![CDATA[To address the bandwidth limitations of the USB 2.0 interface, the USB Implementers Forum (USB-IF) released the SuperSpeed USB 3.0 specifications in November 2008. The USB 3.0 specification provides a maximum bandwidth of up to 5Gbps while limiting power consumption. In this white paper we present the features of the USB 3.0 protocol, discuss the new usage models it enables and compare it with some of the existing interface standards popular in the market today.]]></description>
			<pubDate>Mon, 22 Jun 2009 10:01:00 GMT</pubDate>
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			<title><![CDATA[Updating the High Definition Content Protection Standard with Version 2.0]]></title>
			<link>http://www.design-reuse.com/go2/320936/1</link>
			<description><![CDATA[Al Hawtin (Elliptic Technologies) provides a timely update to the High Definition Content Protection security standard which will shortly be supplemented by HDCP Revision 2.0 and how it will impact delivery over wireless connections. ]]></description>
			<pubDate>Thu, 18 Jun 2009 16:47:00 GMT</pubDate>
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			<title><![CDATA[Viewpoint: Keep design innovation alive]]></title>
			<link>http://www.design-reuse.com/go2/320935/1</link>
			<description><![CDATA[Take a higher level, holistic view of the aims of the entire product design experience. Reassess the design processes you use and how they map into today's technology and your customer's needs.  ]]></description>
			<pubDate>Thu, 18 Jun 2009 16:42:00 GMT</pubDate>
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			<title><![CDATA[SpiritEd: A Register Specification System integrating IP-XACT and Adobe FrameMaker]]></title>
			<link>http://www.design-reuse.com/go2/317309/1</link>
			<description><![CDATA[In this paper, we present a FrameMakerTM based environment that allows the entry of register data together with the remaining specification. Only the registers are captured by a specialized graphical user interface and stored in a XML database using IPXACT.]]></description>
			<pubDate>Thu, 18 Jun 2009 16:20:00 GMT</pubDate>
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			<title><![CDATA[Generic and Automatic Specman based Verification Environment for Image Signal Processing IPs]]></title>
			<link>http://www.design-reuse.com/go2/320907/1</link>
			<description><![CDATA[In this paper, we present a generic and automatic Specman based verification environment for the verification of the image signal processing IPs. Specman based coverage driven random verification is very powerful methodology for the verification of IPs. However, it requires strong knowledge of ‘e’ language. The main aim of development of this verification environment is to more efficiently verify each image signal processing IP (both at module level and sub-system level) which have standard register interface(s) and video data interface(s).]]></description>
			<pubDate>Mon, 15 Jun 2009 15:44:00 GMT</pubDate>
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			<title><![CDATA[Viewpoint: Opportunity to win on different design fronts ]]></title>
			<link>http://www.design-reuse.com/go2/320901/1</link>
			<description><![CDATA[Beyond pure process scaling which is necessary to meet today's price, power, and performance goals, chip designers have to grapple with tighter integration and product performance specialities in areas such as integrated power management, image sensing, application-specific data conversion, and enhanced display drivers.]]></description>
			<pubDate>Mon, 15 Jun 2009 12:57:00 GMT</pubDate>
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			<title><![CDATA[Real-World Reuse: RTL Recycling]]></title>
			<link>http://www.design-reuse.com/go2/317825/1</link>
			<description><![CDATA[This paper presents the theory that a method can be applied to recycling RTL code that in turn leads to a design that can be easily reused on a new project. By applying this method to the very real process of recycling RTL in the context of a new project, the resultant code actually has been designed for reuse]]></description>
			<pubDate>Thu, 11 Jun 2009 17:02:00 GMT</pubDate>
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			<title><![CDATA[Networks-on-Chip with Reprogrammable Interconnections]]></title>
			<link>http://www.design-reuse.com/go2/320887/1</link>
			<description><![CDATA[One of ways for enlargement of ASIC based Systems-on-chip field of application is using of internal interconnection system based on reconfigurable Network-on-chip. In this article we suggest some variants of reconfigurable system-on-chip structure based on physical and virtual channels, evaluate their parameters. We suggest mathematical model for relative hardware cost of systems evaluation We compare hardware cost and throughput for these variants of systems.]]></description>
			<pubDate>Thu, 11 Jun 2009 16:46:00 GMT</pubDate>
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			<title><![CDATA[Tailored SoC Building Using Reconfigurable IP Blocks]]></title>
			<link>http://www.design-reuse.com/go2/320846/1</link>
			<description><![CDATA[Increasing complexity, faster changing standards and shorter time to market ask for composing systems out of standard IP components. An example shows the construction of a System-on-Chip (SoC) based on standard IP components for a Digital Audio Broadcasting consumer application. ]]></description>
			<pubDate>Mon, 08 Jun 2009 10:41:00 GMT</pubDate>
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			<title><![CDATA[Can MIPI and MDDI Co-Exist?]]></title>
			<link>http://www.design-reuse.com/go2/320832/1</link>
			<description><![CDATA[Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?]]></description>
			<pubDate>Mon, 08 Jun 2009 08:10:00 GMT</pubDate>
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			<title><![CDATA[Programmability in portable design: the five modes of motivation ]]></title>
			<link>http://www.design-reuse.com/go2/320836/1</link>
			<description><![CDATA[Wendy Lockhart explains that flash based FPGAs can replace ASICs in portable devices.]]></description>
			<pubDate>Thu, 04 Jun 2009 17:03:00 GMT</pubDate>
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			<title><![CDATA[PRODUCT HOW-TO: Building an FPGA-based Digital Down Converter]]></title>
			<link>http://www.design-reuse.com/go2/320833/1</link>
			<description><![CDATA[When compared on a size/power/cost per channel basis, narrowband, high channel-count DDC cores can be very efficiently implemented in FPGAs. ]]></description>
			<pubDate>Thu, 04 Jun 2009 16:45:00 GMT</pubDate>
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