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		<title>Design And Reuse - Industry Articles</title>
		<link>http://www.design-reuse.com/</link>
		<description>The industry source for engineers and technical managers worldwide.</description>
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		<copyright>Copyright 2007, Design And Reuse S.A.</copyright>
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		<title>Design And Reuse - Industry Articles</title> 
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			<title><![CDATA[Video encoding with low-cost FPGAs for multi-channel H.264 surveillance]]></title>
			<link>http://www.design-reuse.com/go2/319632/1</link>
			<description><![CDATA[Building a high-performance, quad-channel H.264 encoder using low-cost, low-power FPGA architecture.]]></description>
			<pubDate>Mon, 01 Dec 2008 17:12:00 GMT</pubDate>
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			<title><![CDATA[A scalable MIMO near-maximum likelyhood (ML) detector]]></title>
			<link>http://www.design-reuse.com/go2/319633/1</link>
			<description><![CDATA[Here is a novel MIMO near-maximum likelihood (ML) detection technique that is scalable in performance and power. The detector is implemented on a SDR platform and on a TI DSP.]]></description>
			<pubDate>Mon, 01 Dec 2008 14:20:00 GMT</pubDate>
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			<title><![CDATA[Dealing with clock jitter in embedded DDR2/DDR3 DRAM designs: Part 1]]></title>
			<link>http://www.design-reuse.com/go2/319621/1</link>
			<description><![CDATA[This series of three articles explores DDR2/DDR3 clock jitter specifications and provides guidance to embedded systems developers on how to apply them and deal with violations when systems encounter them. Part 1 &quot; Defining Clock Jitter]]></description>
			<pubDate>Thu, 27 Nov 2008 17:21:00 GMT</pubDate>
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			<title><![CDATA[Dealing with clock jitter in embedded DDR2/DDR3 DRAM designs: Part 2]]></title>
			<link>http://www.design-reuse.com/go2/319620/1</link>
			<description><![CDATA[This series of three articles explores DDR2/DDR3 clock jitter specifications and provides guidance to embedded systems developers on how to apply them and deal with violations when systems encounter problems. Part 2: DDR2/DDR3 Functionality]]></description>
			<pubDate>Thu, 27 Nov 2008 17:18:00 GMT</pubDate>
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			<title><![CDATA[Dealing with clock jitter in embedded DDR2/DDR3 DRAM designs: Part 3]]></title>
			<link>http://www.design-reuse.com/go2/319619/1</link>
			<description><![CDATA[This series of three articles explores DDR2/DDR3 clock jitter specifications and provides guidance to embedded systems developers on how to apply them and how to deal with violations when systems encounter them. Part 3: Clock Jitter and Statistics]]></description>
			<pubDate>Thu, 27 Nov 2008 17:16:00 GMT</pubDate>
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			<title><![CDATA[Unified Verification for Hardware and Embedded Software Developers]]></title>
			<link>http://www.design-reuse.com/go2/319611/1</link>
			<description><![CDATA[Moore's Law continues to drive chip complexity and performance to new highs, while stressing and periodically &quot;breaking&quot; existing design flows.]]></description>
			<pubDate>Wed, 26 Nov 2008 08:33:00 GMT</pubDate>
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			<title><![CDATA[Build low power video SoCs with programmable multi-core video processor IP]]></title>
			<link>http://www.design-reuse.com/go2/319597/1</link>
			<description><![CDATA[With power consumption comparable to ASICs, this SoC architecture scales to 1080p and beyond.]]></description>
			<pubDate>Mon, 24 Nov 2008 15:45:00 GMT</pubDate>
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			<title><![CDATA[Analog &amp; Mixed Signal IC Debug: A high precision ADC application]]></title>
			<link>http://www.design-reuse.com/go2/319575/1</link>
			<description><![CDATA[Increasing pressure on production costs and, more generally, time to market, have impacted all levels of IC design. In this context, one of the major challenges is to avoid silicon failure or yield loss.]]></description>
			<pubDate>Thu, 20 Nov 2008 14:40:00 GMT</pubDate>
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			<title><![CDATA[Squeeze power efficiency out of processor-based designs -- Part one]]></title>
			<link>http://www.design-reuse.com/go2/319584/1</link>
			<description><![CDATA[Architect embedded systems following power-saving tips and tricks]]></description>
			<pubDate>Thu, 20 Nov 2008 10:24:00 GMT</pubDate>
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			<title><![CDATA[Solving FPGA I/O pin assignment challenges]]></title>
			<link>http://www.design-reuse.com/go2/319581/1</link>
			<description><![CDATA[Here's a step-by-step methodology to help you pinout complex FPGAs.]]></description>
			<pubDate>Thu, 20 Nov 2008 08:02:00 GMT</pubDate>
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			<title><![CDATA[Planning, adopting and implementing adaptive reuse]]></title>
			<link>http://www.design-reuse.com/go2/319562/1</link>
			<description><![CDATA[If you have to question the reuse benefit, then you should not spend resources making anything reusable. Similarly, no convincing is necessary when reuse becomes a practice weaved into the design process such that when it is built, it gets used with cool efficiency. ]]></description>
			<pubDate>Wed, 19 Nov 2008 09:36:00 GMT</pubDate>
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			<title><![CDATA[What if the IP you are looking for does not exist? ]]></title>
			<link>http://www.design-reuse.com/go2/319503/1</link>
			<description><![CDATA[Designing a modern SoC is in great part a job of selecting and integrating existing IP cores from third parties. This represents a tremendous acceleration and cost reduction in the design process when compared to maintaining a multidisciplinary design team in house.]]></description>
			<pubDate>Mon, 17 Nov 2008 10:04:00 GMT</pubDate>
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			<title><![CDATA[Built-In DMA Engines Unleash Power of PCI Express Switches]]></title>
			<link>http://www.design-reuse.com/go2/319529/1</link>
			<description><![CDATA[Direct memory access (DMA) technology has been around for more than 20 years. DMA has been used principally to offload memory accesses (reading and/or writing) from the CPU in order to enable the processor to focus on computational tasks and increase the performance of embedded and other system designs.]]></description>
			<pubDate>Thu, 13 Nov 2008 16:42:00 GMT</pubDate>
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			<title><![CDATA[Follow guidelines to develop an efficient portable power solution]]></title>
			<link>http://www.design-reuse.com/go2/319528/1</link>
			<description><![CDATA[
This article presents a generic power supply design for an embedded system and examines the function of each module in the design. It also provides guidelines for selection of topologies and components, thermal and packaging aspects, battery management, and hooks that interface the circuit to intelligent power management software.]]></description>
			<pubDate>Thu, 13 Nov 2008 16:36:00 GMT</pubDate>
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			<title><![CDATA[Automotive radio receiver harnesses Software Defined Radio]]></title>
			<link>http://www.design-reuse.com/go2/319494/1</link>
			<description><![CDATA[Auto-qualified, multi-standard digital radio receiver uses software to implement seven standards; signal-processing blocks are functions that can be shared between different standards.]]></description>
			<pubDate>Mon, 10 Nov 2008 16:08:00 GMT</pubDate>
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			<title><![CDATA[Video-image processing with customizable DSP-FPGA platform]]></title>
			<link>http://www.design-reuse.com/go2/319488/1</link>
			<description><![CDATA[An alternative to ASIC, custom processing system, and PC-based video-image processing.]]></description>
			<pubDate>Mon, 10 Nov 2008 14:22:00 GMT</pubDate>
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			<title><![CDATA[Got OCP? The Role of the OCP in Multicore Designs]]></title>
			<link>http://www.design-reuse.com/go2/319484/1</link>
			<description><![CDATA[A brief exposition on the role of the open core protocol (OCP) in system-on-chip designs and the impact of the newest Version 3.0 on the design of multiprocessor SoCs.]]></description>
			<pubDate>Mon, 10 Nov 2008 12:35:00 GMT</pubDate>
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			<title><![CDATA[Changing hardware requires more aggressive testing]]></title>
			<link>http://www.design-reuse.com/go2/319479/1</link>
			<description><![CDATA[Embedded software managers and developers need to rely on more aggressive testing as hardware continues to change.]]></description>
			<pubDate>Thu, 06 Nov 2008 17:05:00 GMT</pubDate>
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			<item>
			<title><![CDATA[Open source in consumer electronics: What, why and how]]></title>
			<link>http://www.design-reuse.com/go2/319478/1</link>
			<description><![CDATA[This article looks at the motives behind open source, explains where open source is (and isn't) succeeding, and reveals Texas Instruments' thinking on Linux and the Open Handset Alliance (OHA).]]></description>
			<pubDate>Thu, 06 Nov 2008 17:01:00 GMT</pubDate>
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			<title><![CDATA[Programmable logic use in handsets--The basics]]></title>
			<link>http://www.design-reuse.com/go2/319456/1</link>
			<description><![CDATA[Today a new generation of low-power FPGAs is enabling a new breed of handset designers to create handsets with features bounded only by imagination. Here's why.]]></description>
			<pubDate>Mon, 03 Nov 2008 17:02:00 GMT</pubDate>
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