Design And Reuse - Industry Articles http://www.design-reuse.com/ The industry source for engineers and technical managers worldwide. en-us Copyright 2007, Design And Reuse S.A. Design And Reuse - Industry Articles http://www.design-reuse.com/IMAGES/dr_rss.gif http://www.design-reuse.com/ <![CDATA[Implementing custom DDR and DDR2 SDRAM external memory interfaces in FPGAs (part 1) ]]> http://www.design-reuse.com/go2/322977/1 Thu, 18 Mar 2010 16:40:00 GMT <![CDATA[Verification of USB 3.0 Device IP Core in Multi-Layer SystemC Verification Environment ]]> http://www.design-reuse.com/go2/322947/1 Mon, 15 Mar 2010 14:28:00 GMT <![CDATA[A Flexible, Field-programmable ROM Replacement]]> http://www.design-reuse.com/go2/322942/1 Mon, 15 Mar 2010 10:39:00 GMT <![CDATA[Viewpoint: Your future is programmable]]> http://www.design-reuse.com/go2/322924/1 Thu, 11 Mar 2010 15:57:00 GMT <![CDATA[Initial Investigations into UML Based Architectural Reference Patterns for Set-Top Boxes ]]> http://www.design-reuse.com/go2/322897/1 Mon, 08 Mar 2010 15:24:00 GMT <![CDATA[Selecting an embedded MCU: How to avoid evaluation trap? ]]> http://www.design-reuse.com/go2/322878/1 Mon, 08 Mar 2010 14:40:00 GMT <![CDATA[Decompiling the ARM architecture code]]> http://www.design-reuse.com/go2/322896/1 Mon, 08 Mar 2010 14:35:00 GMT <![CDATA[Viewpoint: The importance of FPGA-to-ASIC solutions to accelerate CPU-based protocols ]]> http://www.design-reuse.com/go2/322876/1 Thu, 04 Mar 2010 16:20:00 GMT <![CDATA[Embedded Symmetric MultiProcessing system on a SoC with 1.6GHz PowerPC IP in 45nm]]> http://www.design-reuse.com/go2/322839/1 Mon, 01 Mar 2010 10:34:00 GMT <![CDATA[Evolving to a Total IP Solutions to Accelerate SoC Design]]> http://www.design-reuse.com/go2/322838/1 Mon, 01 Mar 2010 09:51:00 GMT <![CDATA[Time to market is a critical consideration]]> http://www.design-reuse.com/go2/322852/1 Mon, 01 Mar 2010 04:53:00 GMT <![CDATA[Software Architecture for IP verification in Operating System environment]]> http://www.design-reuse.com/go2/322825/1 Thu, 25 Feb 2010 15:26:00 GMT <![CDATA[Hardware Solutions to the Challenges of Multimedia IP Functional Verification]]> http://www.design-reuse.com/go2/322786/1 Mon, 22 Feb 2010 15:47:00 GMT <![CDATA[High-level synthesis, verification and language ]]> http://www.design-reuse.com/go2/322796/1 Mon, 22 Feb 2010 11:10:00 GMT <![CDATA[Analog and Mixed Signal Modeling Approaches]]> http://www.design-reuse.com/go2/322773/1 Mon, 22 Feb 2010 10:06:00 GMT <![CDATA[Reusable VHDL IP in the Real World]]> http://www.design-reuse.com/go2/322768/1 Thu, 18 Feb 2010 14:28:00 GMT <![CDATA[My FPGA's not working: Problems with the IP]]> http://www.design-reuse.com/go2/322764/1 Thu, 18 Feb 2010 11:39:00 GMT <![CDATA[Guidelines for complex SoC verification ]]> http://www.design-reuse.com/go2/322750/1 Tue, 16 Feb 2010 16:48:00 GMT