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		<title>Design And Reuse - Headline News</title>
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		<title>Design And Reuse - Industry Expert Blogs</title> 
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			<title><![CDATA[Dual-play gaming on the same 3D TV using HDMI (The Eyes Have it : A Mixed-signal IP Blog - Navraj Nandra, Synopsys)]]></title>
			<link>http://www.design-reuse.com/go2/729288/1</link>
			<description><![CDATA[“Dual Play” gaming allows two players to use the same TV to see two different pictures. Using a 3D TV, dual play allows 2D viewing of the same game for two players on a 3D screen . This way it stops cheating between the players. One player has the left part of the 3D screen, the other player the right.  Using Synopsys’ HDMI compliant 1.4b, 3D video mode technology, allows the Game Console to send the information about content being transmitted, like a 3D with dual-player game.<br>View the full article <a href="http://www.design-reuse.com/go2/729288/1">HERE</a>]]></description>
			<pubDate>Mon, 21 May 2012 09:22:00 GMT</pubDate>
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			<title><![CDATA[DSP IP core? CEVA is the undisputed worldwide leader, with 90% market share (SemiWiki - Eric Esteve)]]></title>
			<link>http://www.design-reuse.com/go2/729285/1</link>
			<description><![CDATA[Anybody working in the wireless handset segment probably knows that CEVA is the provider of DSP IP cores, and if you are simply a wireless handset user, you should know that the baseband digital signal processing is the function allowing your phone to process the RF (analog) signal coming from the outside world. If you have been involved in the wireless segment before 2002, you may remember a company named DSP Group: the merge of the IP licensing division of DSP Group and Parthus has been named CEVA, and CEVA has enjoyed 90% market share for DSP IP products in 2011, according with the Linley Group. A 90% market share simply means that CEVA’ DSP IP have been integrated into 1 billion IC shipped in production in 2011!<br>View the full article <a href="http://www.design-reuse.com/go2/729285/1">HERE</a>]]></description>
			<pubDate>Fri, 18 May 2012 17:28:00 GMT</pubDate>
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			<title><![CDATA[MIPS' Aptiv: Will New Core Families Make the Company More Competitive? (Inside DSP - BDTi)]]></title>
			<link>http://www.design-reuse.com/go2/729284/1</link>
			<description><![CDATA[Processor core provider MIPS Technologies has seemingly fallen on hard times in recent years. Consider, for example, a report published by the Linley Group just last week that indicated chief competitor ARM supplied CPU cores used in 78% of the estimated 10 billion CPU cores in SoCs shipped last year. ARM's estimated per-core license price was 4.6 cents, versus 7 cents for MIPS. However, with MIPS licensees shipping only 665 million MIPS cores (6% of the market, in third place, behind Synopsys/ARC at 10%), MIPS’ revenues trail far behind ARM’s.<br>View the full article <a href="http://www.design-reuse.com/go2/729284/1">HERE</a>]]></description>
			<pubDate>Fri, 18 May 2012 17:26:00 GMT</pubDate>
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			<title><![CDATA[Ivy Bridge: Intel's CPUs Gain a Generational Lithography Edge (Inside DSP - BDTi)]]></title>
			<link>http://www.design-reuse.com/go2/729283/1</link>
			<description><![CDATA[Jerry Sanders, AMD's brash former CEO, once opined, &quot;Real men have fabs. These fabless guys are nobodies, just boys.&quot; In recent times, however, Sanders' comments seemed increasingly antiquated, with various foundries (most notably mighty TSMC) serving the fabrication needs of an increasing number and variety of semiconductor device suppliers. A notable number of those suppliers had historically handled their own manufacturing but eventually decided to mothball their fabs and rely on foundries instead. To wit, AMD announced its intent in late 2008 to spin off the chip-manufacturing portion of its business into a separate entity, originally (and unoriginally) called &quot;The Foundry Company&quot; but later renamed Globalfoundries.<br>View the full article <a href="http://www.design-reuse.com/go2/729283/1">HERE</a>]]></description>
			<pubDate>Fri, 18 May 2012 17:24:00 GMT</pubDate>
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			<title><![CDATA[Semico Conference: &quot;System Driven” Semiconductor IP Leads to IP Subsystems (Industry Insights Blog - Richard Goering , Cadence)]]></title>
			<link>http://www.design-reuse.com/go2/729279/1</link>
			<description><![CDATA[By Richard Goering on May 17, 2012Comments(0)Filed under: Industry Insights, 3D ICs, SoC, Semico, IP, Kapoor, IP quality, system on chip, PCI Express, semiconductor IP, PCIe, silicon IP, 3D-ICs, NVM Express, NVMe, IP subsystems, system-driven IP, Impact, Feldhan, IP ecosystem, design factory A &quot;new breed&quot; of semiconductor intellectual property (IP) is required for the next stage of evolution in the IP ecosystem, according to a keynote speech by Vishal Kapoor (right) of Cadence at the Semico Impact Conference May 16, 2012. This new type of IP will be &quot;system driven,&quot; and it will include IP subsystems, which was also the topic of a panel discussion that followed the keynote. Kapoor is vice president of marketing for SoC Realization at Cadence. The Impact Conference, held in San Jose, California, was a day-long event about the IP ecosystem that included five keynotes and two panels. In addition to IP subsystems, topics included IP ecosystem collaboration, realizing more value for IP, the roles of big and small IP providers, IP quality, and IP for 3D-ICs.<br>View the full article <a href="http://www.design-reuse.com/go2/729279/1">HERE</a>]]></description>
			<pubDate>Fri, 18 May 2012 16:49:00 GMT</pubDate>
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			<title><![CDATA[Who Wins in the IP Ecosystem? (Semico Spin - Adrienne Downey)]]></title>
			<link>http://www.design-reuse.com/go2/729275/1</link>
			<description><![CDATA[Mahesh Tirupattur, Executive Vice President of Analog Bits, led the panel “Who Wins in the IP Ecosystem?” during the Semico Impact 2012.&amp;nbsp; Other members of the panel were Suk Lee of TSMC, Jean-Marie Brunet of Mentor Graphics, Tony Stelliga of Intersil, and Dr. Naveed Sherwani of Open-Silicon. Mr. Tirupattur began the panel by describing today’s industry as a collaborative model, where customers tell the IP companies what they want, and what they can do better.&amp;nbsp; What the industry needs is a dynamic ecosystem that improves efficiency, with no waste or redundancy.&amp;nbsp; It’s not just who wins in the ecosystem, but how do we get paid for the value we bring to the table?<br>View the full article <a href="http://www.design-reuse.com/go2/729275/1">HERE</a>]]></description>
			<pubDate>Thu, 17 May 2012 15:41:00 GMT</pubDate>
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			<title><![CDATA[Foundry and IP Business Model: Alive and Well (ARM Blogs - John Heinlein)]]></title>
			<link>http://www.design-reuse.com/go2/729274/1</link>
			<description><![CDATA[In my role, I serve as one of the members of the Global Semiconductor Alliance (GSA) Steering Committee on Intellectual Property, where we work to share best practices and continue to improve the IP ecosystem for the benefit of the entire semiconductor industry. As part of this role, I’ve observed a trend in the news speculating on the future of the foundry and IP industry, and I recently posted my thoughts on the GSA blog site, and I’d like to share them with you here as well. In 1897, after a journalist erroneously reported the passing of famed author and humorist Mark Twain, Twain replied in his typical wit with the now famous retort “The rumor of my death has been greatly exaggerated.” Like the then very alive author, recent reports have speculated on the demise of the foundry and IP business model. I similarly think such talk is pure nonsense. Across many metrics the foundry and IP space is alive and well and providing unprecedented capabilities to semiconductor companies. Let’s put the tabloid down and look at the facts from a few different perspectives.<br>View the full article <a href="http://www.design-reuse.com/go2/729274/1">HERE</a>]]></description>
			<pubDate>Thu, 17 May 2012 07:53:00 GMT</pubDate>
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			<title><![CDATA[MIPS, ARM, ARC, Imagination, Ceva (SemiWiki - Paul McLellan)]]></title>
			<link>http://www.design-reuse.com/go2/729269/1</link>
			<description><![CDATA[The Linley Group, whose conference on mobile I recently attended, has some interesting data about the processor core market. Firstly, the numbers are big: CPU cores shipped in over 10 billion chips last year which is up 25% on last. ARM has a share of 78% of that entire market. The big surprise to me was the #2 was not MIPS but Synopsys with the ARC processor that they acquired with Virage. They have a 10% share. MIPS can only manage 6%. ARM licensees shipped 7.9 billions chips on which ARM collected an average royalty of 4.6¢ down a little from 4.8¢ the year before. By contrast, MIPS licensees shipped just 650M chips although they made around 7¢ per chip.<br>View the full article <a href="http://www.design-reuse.com/go2/729269/1">HERE</a>]]></description>
			<pubDate>Wed, 16 May 2012 09:20:00 GMT</pubDate>
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			<title><![CDATA[$800M says Thunderbolt stays Closed (To USB or Not to USB: A USB IP Blog - Eric Huang, Synopsys)]]></title>
			<link>http://www.design-reuse.com/go2/729268/1</link>
			<description><![CDATA[I’m constantly asked: &quot;Will Thunderbolt replace USB 3.0?&quot; Thunderbolt and USB 3.0 will co-exist &amp;amp; live long, fruitful lives As reported previously, Apple filed and recieved a patent for a new iPhone or iPad connector which looks&amp;nbsp; like a Thunderbolt connection. You can see in the picture that it includes connections for USB 3.0 and dual port Displayport. <br>View the full article <a href="http://www.design-reuse.com/go2/729268/1">HERE</a>]]></description>
			<pubDate>Wed, 16 May 2012 09:05:00 GMT</pubDate>
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			<title><![CDATA[Solving the challenge of embedded IP test (The Eyes Have it : A Mixed-signal IP Blog - Navraj Nandra, Synopsys)]]></title>
			<link>http://www.design-reuse.com/go2/729267/1</link>
			<description><![CDATA[Not a topic I usually write about but having a beer with Dr. Yervant Zorian during our recent Synopsys Users’ Group, got me thinking about the challenge of testing embedded IP, that is IP like a USB or DDR that is embedded in one of our customer’s chips.&amp;nbsp;The challenge becomes compounded when multiple IP’s are integrated with different test access strategies, different test interfaces and different mechanisms to describe test patterns. The good news is that Yervant and his team have been looking at this problem&amp;nbsp; and here is a summary from&amp;nbsp;Gevorg Torjyan.<br>View the full article <a href="http://www.design-reuse.com/go2/729267/1">HERE</a>]]></description>
			<pubDate>Wed, 16 May 2012 08:59:00 GMT</pubDate>
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			<title><![CDATA[The Facts: Why Accelerated VIP Is Needed for SoC Verification (Functional Verification Blog - Peter Heller)]]></title>
			<link>http://www.design-reuse.com/go2/729265/1</link>
			<description><![CDATA[On Tuesday May 15th Cadence announced the expansion of our VIP Catalog to include accelerated VIP (AVIP).&amp;nbsp; You may be wondering why Cadence is investing in accelerated VIP (which runs on an accelerated platform such as the Palladium XP) when we already have the market leading simulation VIP.&amp;nbsp; Good question.&amp;nbsp; This blog will answer that and explain the rationale behind Cadence's AVIP and more about our products and plans going forward.&amp;nbsp;  A key driving factor impacting verification approach is the size of the design.&amp;nbsp; Today designs commonly are in the 10's and even 100's of millions of gates.&amp;nbsp; And software size is growing at an even faster pace.&amp;nbsp; There's no respite in sight for these torrid growth rates.&amp;nbsp; So even if you don't face such verification challenges immediately, read on, because they're coming.&amp;nbsp;&amp;nbsp;&amp;nbsp; <br>View the full article <a href="http://www.design-reuse.com/go2/729265/1">HERE</a>]]></description>
			<pubDate>Tue, 15 May 2012 16:53:00 GMT</pubDate>
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			<title><![CDATA[How IP Subsystem Will Speed NVM Express (NVMe) Adoption (Industry Insights Blog - Richard Goering , Cadence)]]></title>
			<link>http://www.design-reuse.com/go2/729261/1</link>
			<description><![CDATA[Non-Volatile Memory Express (NVM Express or NVMe) is an emerging protocol standard for accessing solid state drives (SSDs) over PCI Express (PCIe) links. It would thus make sense, if you're designing an SoC that has an SSD interface, to cobble together a subsystem that includes an NVMe controller, PCIe controller, and PCIe PHY. But what if you could just buy a configurable subsystem that includes all of these components running under a common firmware layer? <br>View the full article <a href="http://www.design-reuse.com/go2/729261/1">HERE</a>]]></description>
			<pubDate>Tue, 15 May 2012 15:50:00 GMT</pubDate>
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			<title><![CDATA[Unicorns, Leprechauns and Reusable Verification IP (AgileSoC  - Neil Johnson)]]></title>
			<link>http://www.design-reuse.com/go2/729254/1</link>
			<description><![CDATA[There are times when I use agilesoc.com to step out on a limb and challenge the general consensus in hardware development. This post would definitely qualify as one of those times. I don’t think the reusable verification IP we’ve been building is as reusable as we think it is. I don’t think reusable IP is reused as many times as we’d like (if at all). Nor do I think reusable IP is as valuable as we think it is. There… I said it. That hasn’t always been my opinion… in fact I used to be a person that preached the exact opposite… but that’s my opinion now and it feels good to get it out. <br>View the full article <a href="http://www.design-reuse.com/go2/729254/1">HERE</a>]]></description>
			<pubDate>Tue, 15 May 2012 09:24:00 GMT</pubDate>
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			<title><![CDATA[Moore's Law: Wanted, Dead or Alive (EDA360 Insider - Steve Leibson)]]></title>
			<link>http://www.design-reuse.com/go2/729252/1</link>
			<description><![CDATA[Moore’s Law is not dead but the vital signs have clearly changed. That was the key message I heard from Dr. Subramanian Iyer, Fellow and Chief Technologist at the IBM Systems &amp;amp; Technology Group, during the GSA Silicon Summit held on April 26 at the Computer History Museum in Mountain View, California. Iyer pointed out that process complexity has grown from node to node. Yes we already knew that—but in earlier node transitions the increased processing cost was offset by the doubled number of additional transistors per unit area you get for each jump. Iyer projected a graph showing that the reduced effective cost per transistor stops falling after the 32/28nm node. Here’s the graph:<br>View the full article <a href="http://www.design-reuse.com/go2/729252/1">HERE</a>]]></description>
			<pubDate>Tue, 15 May 2012 08:51:00 GMT</pubDate>
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			<title><![CDATA[TSMC Tops Intel, Samsung in Capacity! (SemiWiki - Daniel Nenni)]]></title>
			<link>http://www.design-reuse.com/go2/729237/1</link>
			<description><![CDATA[While I was marlin fishing in Hawaii last week I missed some interesting comments from TSMC executives at the Technology Symposium in Taiwan, a much different show than the one here in San Jose I’m told. It is good to see TSMC setting the record straight and taking a little credit for what they have accomplished! I’m sorry I missed it but I know quite a few people who didn’t and they were quite impressed.<br>View the full article <a href="http://www.design-reuse.com/go2/729237/1">HERE</a>]]></description>
			<pubDate>Mon, 14 May 2012 09:44:00 GMT</pubDate>
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			<title><![CDATA[USB 3.0 Docking Stations Replace all Others - Starting Now (To USB or Not to USB: A USB IP Blog - Eric Huang, Synopsys)]]></title>
			<link>http://www.design-reuse.com/go2/729236/1</link>
			<description><![CDATA[The Fujitsu, ThinkPad, and Targus USB 3.0 Docking Stations represent the first of future Docking stations.&amp;nbsp; These units will completely replace the existing docking stations on your desktop within the next 3 years.<br>View the full article <a href="http://www.design-reuse.com/go2/729236/1">HERE</a>]]></description>
			<pubDate>Mon, 14 May 2012 09:41:00 GMT</pubDate>
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			<title><![CDATA[Reversal from the foundry model back to IDM ? (EETimes Blog - Zvi Or-Bach, MonolithIC 3D Inc. )]]></title>
			<link>http://www.design-reuse.com/go2/729235/1</link>
			<description><![CDATA[Recently Rick Merritt of EE Times reported on his interview with Mark Bohr, &quot;Mr. Process Technology at Intel,&quot; and wrote: &quot;It’s the beginning of the end for the fabless model according to Mark Bohr.&quot; Quite naturally this caused many responses, with the majority of them hinting that Intel is trying to break into the smart mobile space by sowing doubt in the future of the existing ecosystem around TSMC-ARM and multiple fabless vendors.<br>View the full article <a href="http://www.design-reuse.com/go2/729235/1">HERE</a>]]></description>
			<pubDate>Mon, 14 May 2012 08:43:00 GMT</pubDate>
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			<title><![CDATA[Logic Built-in Self Test (LBIST) is Back - But Not for Manufacturing Test (Industry Insights Blog - Richard Goering , Cadence)]]></title>
			<link>http://www.design-reuse.com/go2/729220/1</link>
			<description><![CDATA[Memory providers have long used built-in self test (BIST), a technology that builds self-testing circuitry directly into an IC. Logic BIST (LBIST), which tests the functional logic, has been around for a while too -- but it&amp;nbsp;did not get much traction except&amp;nbsp;for some high-end CPU server and networking chips. Now, LBIST is back -- but generally not for manufacturing test, as you might expect. First, some quick background. An LBIST macro, as shown below, includes a pseudorandom pattern generator (PRPG) and a multiple-input shift register (MISR). The LBIST macro generates and runs stimulus derived from a seed, and then checks &quot;signatures&quot; of bits to verify the expected operation of the circuit. The stimulus can be driven over scan chains. LBIST can use JTAG circuitry to initiate the testing, or it can use a direct method where a pin changes state and LBIST automatically runs.<br>View the full article <a href="http://www.design-reuse.com/go2/729220/1">HERE</a>]]></description>
			<pubDate>Thu, 10 May 2012 15:55:00 GMT</pubDate>
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			<title><![CDATA[Fujitsu, Lenovo USB 3.0 Docking Stations, Fast USB 3.0 Flash Drive Dialog (To USB or Not to USB: A USB IP Blog - Eric Huang, Synopsys)]]></title>
			<link>http://www.design-reuse.com/go2/729238/1</link>
			<description><![CDATA[Fujitsu and Lenovo announced USB 3.0 Docking Stations both using the DisplayLink USB 3.0 to HDMI chip.<br>View the full article <a href="http://www.design-reuse.com/go2/729238/1">HERE</a>]]></description>
			<pubDate>Thu, 10 May 2012 09:46:00 GMT</pubDate>
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			<title><![CDATA[A Giant Leap for the Android Ecosystem (MIPS Technologies Blog - Amit Rohatgi, Principal Mobile Architect, MIPS Technologies)]]></title>
			<link>http://www.design-reuse.com/go2/729212/1</link>
			<description><![CDATA[On May 1, Google released an update to its Native Development Kit (NDK) that allows for the creation of native apps that run on MIPS-Based devices. This is a big deal! Google took notice of the millions of MIPS-Based Android devices and took action to include support for the MIPS ABI. While developers in the past have been able to obtain a MIPS NDK from the MIPS developer site, they can now get it from the main Android developer site—where the vast majority of developers obtain the NDK. With this move, we expect many new developers will begin pushing out MIPS-compatible apps in very short time.<br>View the full article <a href="http://www.design-reuse.com/go2/729212/1">HERE</a>]]></description>
			<pubDate>Wed, 09 May 2012 16:36:00 GMT</pubDate>
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