Build low power video SoCs with programmable multi-core video processor IP

By P V Suresh Babu, Director, Squid Design Systems
videsignline.com (November 21, 2008)

Multimedia applications are expanding constantly. With the advent of mobile Internet, mobile TV and the availability of huge bandwidth through broadband networks, market demand for new multimedia applications such as mobile Internet devices, portable media players and IPTV set top boxes is growing rapidly. Similarly, social networking, VOD and user-generated video content have created a need for generic video processing architectures that support higher video resolutions such as SD and HD, and flexibility to host multiple applications like video playback, recording, transcoding and editing.

Most battery operated devices use fixed function video ASICs that tend to restrict application flexibility for the sake of obtaining a power consumption advantage. This sacrifice is not necessary. Programmable video architecture designs which consider area optimization, power optimization and programmability, and use proprietary data flow processing techniques, bring the advantages of flexibility to incorporate new features, with power consumption equivalent to ASIC implementations. A programmable video architecture provides the flexibility and capability to add new applications such as editing and transcoding, apart from video playback and recording.

To bring high resolution video processing and support for various features, SoC designers must optimize the power consumption of all components within the application. Keeping in mind present and future application demands, flexibility is also a key requirement for the video processing IP.

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